Fin Structure Dielectric Shell for Lower Parasitic Capacitance
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Solution Overview
Problem
The increase in parasitic capacitance between adjacent fins in Fin FETs degrades circuit speed and reduces device performance, posing a challenge in semiconductor manufacturing.
Innovation Solution
A method involving the formation of fin structures with alternating semiconductor layers, followed by the deposition of dielectric layers and sacrificial cladding layers, and subsequent annealing and etching processes to reduce capacitance, including the use of high-k dielectric materials and oxide insertion layers to form a crystalline shell around the dielectric layers, thereby reducing metal gate capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If fin structures are placed closer together to increase device density, then device density is improved, but parasitic capacitance between adjacent fins increases
Solution Approach 1:
A dielectric layer is introduced as an intermediary material between adjacent fin structures. This dielectric layer acts as a mediator that reduces the electrical coupling (parasitic capacitance) between fins while allowing the fins to remain in close proximity for high device density. The dielectric material with appropriate permittivity properties provides electrical isolation between fins.
Solution Approach 2:
The patent applies different material properties to different regions: the dielectric layer is specifically positioned in the regions between adjacent fins where parasitic capacitance occurs, while the fin structures themselves maintain their conductive properties. This localized application of different material qualities addresses the capacitance issue without compromising the overall device functionality.
2Ease of manufacture
If conventional dielectric materials are used between fins, then manufacturing is simplified, but parasitic capacitance remains high degrading circuit speed
Solution Approach 1:
The patent changes the electrical parameter (permittivity/dielectric constant) of the material between fins by selecting a dielectric material with optimized properties. This parameter change reduces the capacitance value while maintaining compatibility with existing manufacturing processes, thereby improving circuit speed without sacrificing ease of manufacture.
3Productivity
If device density is increased by reducing fin spacing, then productivity is improved, but electrical interference between adjacent fins increases
Solution Approach 1:
The dielectric layer serves as an intermediary that provides electrical isolation between closely spaced fins. This mediator reduces capacitive coupling and minimizes electrical interference (such as crosstalk) between adjacent fins, enabling higher device density without compromising signal integrity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces parasitic capacitance, enhancing circuit speed and overall device performance by minimizing electrical interference between adjacent fins.
Implementation Method 1
performing an annealing operation to convert a portion of the one or more layers of the first dielectric layer and the insertion layer from an amorphous form to a crystalline form
Data Source
AI summary
A method of manufacturing a semiconductor device includes forming a fin structure including a stacked layer of first semiconductor layers and second semiconductor layers disposed over a bottom fin structure and a hard mask layer over the stacked layer, forming an isolation insulating layer so that the hard mask layer and the stacked layer are exposed from the isolation insulating layer, forming a sacrificial cladding layer over at least sidewalls of the exposed hard mask layer and stacked layer, forming layers of a first dielectric layer and an insertion layer over the sacrificial cladding layer and the fin structure, performing an annealing operation to convert a portion of the layers of the first dielectric layer and the insertion layer from an amorphous form to a crystalline form, and removing the remaining amorphous portion of the layers of the first dielectric layer and the insertion layer to form a recess.