Semiconductor Fin Ditches for Drive Current Enhancement

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Solution Overview

Problem

Current methods for improving drive currents in Fin Field-Effect Transistors (FinFETs) using Germanium, Silicon Germanium, and III-V compound semiconductors do not effectively enhance on-current without increasing the recessing depth, which complicates the manufacturing process and increases costs.

Innovation Solution

The formation of ditches near semiconductor fins in STI regions using a germanium-containing layer and subsequent annealing to create a differential etching rate, allowing for increased fin height without additional etching or lithography steps, thereby enhancing on-current without increasing the recessing depth.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the recessing depth is increased to enhance on-current, then the drive current improves, but the manufacturing process complexity and costs increase

Engineering Contradiction:
Improvedrive currentVSAvoidmanufacturing process complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent introduces ditches with different etching rates at specific locations near the fin structures. By creating local variations in material composition (using germanium-containing layers) and corresponding etching rates, the fin height is selectively increased in critical areas without requiring uniform increases throughout the entire structure, thus improving drive current while avoiding proportional increases in overall process complexity

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The germanium-containing layers are deposited and annealed in advance to create the differential etching rate structure before the final fin formation process. This preliminary preparation enables the subsequent etching step to automatically produce the desired fin height variations without requiring additional lithography or etching steps, thereby resolving the contradiction between achieving higher drive currents and maintaining process simplicity

Inventive Principle:
Principle #10Preliminary action

2Productivity

If additional etching or lithography steps are added to increase fin height, then on-current enhances, but manufacturing costs increase

Engineering Contradiction:
Improveon-currentVSAvoidmanufacturing cost
Core Design Contradiction:
ProductivityVSEase of manufacture

Solution Approach 1:

The structure utilizes self-aligned formation where the ditches are automatically positioned relative to the fins through the etching process itself. The germanium-containing layers serve as both the material for creating differential etching rates and as a guide for where the ditches should form, eliminating the need for separate alignment and positioning steps that would otherwise be required, thus avoiding additional manufacturing costs while achieving the desired fin height increase

Inventive Principle:
Principle #25Self-service

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach increases the on-current of FinFETs by enhancing the fin height through the formation of ditches in STI regions, resulting in higher drive currents while maintaining process simplicity and reducing manufacturing costs.

Implementation Method 1

subsequent annealing to create a differential etching rate

Methodology Applied
Scientific EffectAnnealing: Annealing

Data Source

PatentUS20140264608A1Ditches near semiconductor fins and methods for forming the same
Publication Date: 2014.09.18 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20140264608A1 patent drawing
  • US20140264608A1 patent drawing
  • US20140264608A1 patent drawing

AI summary

A device includes a semiconductor substrate, and isolation regions extending into the semiconductor substrate. A semiconductor strip is between and contacting the isolation regions. A semiconductor fin overlaps, and is joined to, the semiconductor strip. A ditch extends from a top surface of the isolation regions into the isolation regions, wherein the ditch adjoins the semiconductor fin.