Semiconductor Fin Doping Layout to Avoid PMOS Implant Damage
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Solution Overview
Problem
The scaling of multi-gate transistors in integrated circuits leads to constraints in semiconductor processes, particularly due to sub-amorphous damage from N-Well implants, which degrades PMOS drive current, and existing solutions like hot implant and IAIA are costly and complex to integrate.
Innovation Solution
Implementing a non-patterned N-Well implant before fin formation, followed by a patterned P-Well implant at double the traditional dose, to compensate N-Well doping and provide P-doping, thereby eliminating damage and reducing costs and complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional N-Well implant is performed before fin formation, then PMOS device isolation is achieved, but sub-amorphous damage occurs that degrades PMOS drive current
Solution Approach 1:
The patent performs the N-Well implant before fin formation, allowing the damage to occur in the bulk silicon where it can be healed by subsequent thermal processing, rather than after fin formation where the fins are already formed and vulnerable. This preliminary timing of the implant allows for damage recovery without compromising the fin structure.
Solution Approach 2:
The patent changes the timing parameter of when the N-Well implant is performed relative to fin formation, and adjusts the subsequent thermal processing parameters to heal the damage. By modifying these process parameters and their sequence, the harmful effects are mitigated while maintaining the necessary doping profile.
2Reliability
If hot implant or IAIA methods are used to compensate N-Well damage, then PMOS drive current is improved, but process cost and complexity increase
Solution Approach 1:
The patent extracts and eliminates the need for complex hot implant or IAIA compensation steps by performing the N-Well implant at the optimal time before fin formation. This removes the harmful damage before it can affect the fins, making subsequent compensation steps unnecessary and simplifying the overall process.
Solution Approach 2:
By performing the N-Well implant before fin formation and followed by thermal processing to heal damage, the patent preliminarily addresses the damage issue before it affects the critical fin structures. This preliminary action eliminates the need for later complex compensation steps.
3Productivity
If feature size is scaled down to increase device density, then chip capacity increases, but process constraints become overwhelming
Solution Approach 1:
The patent performs the N-Well implant before fin formation, preliminarily establishing the doping profile in the bulk silicon. This timing allows subsequent fin formation and processing to proceed without the complicating factor of pre-existing damage, simplifying the overall scaled process.
Solution Approach 2:
The patent changes the process sequence parameters for scaled devices, performing the implant at a different stage relative to fin formation. This parameter change adapts the process to scaling requirements by preventing damage accumulation that would be more problematic at smaller dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach achieves double-digit drive current gains for single-fin PMOS devices and high-single digit gains for 2 and 3-fin devices, while providing cost savings and eliminating implant damage, with lower implant energies and simpler integration compared to traditional methods.
Implementation Method 1
N-Well implants
Implementation Method 2
patterned P-Well implant
Data Source
AI summary
Fin doping, and integrated circuit structures resulting therefrom, are described. In an example, an integrated circuit structure includes a semiconductor fin. A lower portion of the semiconductor fin includes a region having both N-type dopants and P-type dopants with a net excess of the P-type dopants of at least 2E18 atoms/cm3. A gate stack is over and conformal with an upper portion of the semiconductor fin. A first source or drain region is at a first side of the gate stack, and a second source or drain region is at a second side of the gate stack opposite the first side of the gate stack.