Fin Structures via Directed Self Assembly Lithography
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Solution Overview
Problem
Current techniques for producing fin structures in semiconductor devices, such as self-aligned double patterning (SADP) and Directed Self Assembly (DSA), face limitations in achieving fin pitches smaller than 10 nm, with SADP reaching its limits and DSA suffering from alignment issues and increased line edge roughness.
Innovation Solution
A method using DSA lithographic patterning in conjunction with a shallow trench isolation layer stack and a hard mask layer to define fin structures, involving specific layer stacks and etching processes to achieve fin pitches smaller than 10 nm, including the use of DSA layer stacks and photoresist layers for pattern transfer and surface flattening.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If SADP technique is used for defining fin structures, then fin pitch can be reduced to 10 nm, but further reduction below 10 nm is not achievable without EUV lithography
Solution Approach 1:
The patent segments the patterning process into multiple steps: first forming mandrel structures at a relaxed pitch, then using spacer deposition and removal cycles to multiply the pattern density. This segmentation allows achieving sub-10nm fin pitch without requiring EUV lithography, as each step operates at achievable process nodes while the cumulative effect achieves the target precision
Solution Approach 2:
The patent performs preliminary actions by first forming the mandrel structures and spacer layers before the actual fin definition. The dummy core structures and spacer materials are prepared in advance with specific dimensions and materials selected to enable subsequent etching and pattern transfer steps that will achieve the final sub-10nm fin pitch
2Manufacturing precision
If DSA technique is used for forming fin structures below 10 nm, then finer pitches can be achieved, but alignment issues and increased line edge roughness occur
Solution Approach 1:
The patent introduces intermediary structures (mandrels and spacers) that mediate between the lithography step and the final fin pattern. The mandrel structures serve as intermediate templates that are easier to align, and the spacer layers act as intermediaries that transfer the pattern with reduced line edge roughness, thereby improving alignment precision while enabling sub-10nm fin pitch
Solution Approach 2:
The patent changes material parameters by selecting specific materials for mandrels and spacers with controlled deposition thicknesses and etch selectivities. By adjusting spacer thickness, mandrel dimensions, and material composition, the process optimizes the self-aligned nature of the pattern transfer, reducing alignment issues and line edge roughness while achieving the required fin pitch precision
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the production of fin structures with pitches smaller than 10 nm, improving alignment and reducing line edge roughness, thereby overcoming the limitations of existing methods and achieving precise semiconductor device patterning.
Implementation Method 1
The BCP layer is spin coated and annealed leading to the self-organization of the polymer constituents according to the pre-mask pattern
Implementation Method 2
DSA lithographic patterning is a lithography technique in which a mask layer is produced by means of a directed self-assembly process
Implementation Method 3
The pre-mask layer (e.g., X-PS layer) is deposited over the surface and patterned by using a photoresist and an associated lithography step
Implementation Method 4
After removal of one of the polymer constituents by selective etching, e.g. the PMMA component, the pattern is ready to be transferred into the underlying layer(s)
Data Source
AI summary
A method for producing fin structures, using Directed Self Assembly (DSA) lithographic patterning, in an area of a semiconductor substrate includes providing a semiconductor substrate covered with a shallow trench isolation (STI) layer stack on a side thereof; defining a fin area on that side of the substrate by performing a lithographic patterning step other than DSA, wherein the fin structures will be produced in the fin area; and producing the fin structures in the semiconductor substrate within the fin area according to a predetermined fin pattern using DSA lithographic patterning. The disclosure also relates to associated semiconductor structures.