Fin Dual Liner Thickness Variation for Current Control
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Solution Overview
Problem
In semiconductor devices, the scaling of gate all around structures is limited by the short channel effect, which affects the potential of the channel region due to drain voltage, and current control is challenging without increasing the two-dimensional width of the gate.
Innovation Solution
The semiconductor device features fins with dual liners and an epitaxial layer, where the liners have different thicknesses, and the epitaxial layer surrounds the top portion of one fin, allowing for varying widths and preventing changes in fin critical dimensions, enabling effective current control and reduced short channel effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate all around structures are scaled down to improve current control and suppress short channel effects, then transistor performance is improved, but manufacturing precision becomes more difficult to maintain
Solution Approach 1:
The fin structure is segmented into different regions with different liner thicknesses - the first liner has a first thickness and the second liner has a second thickness greater than the first thickness. This segmentation allows different portions of the fin to be protected with appropriate liner thicknesses, maintaining manufacturing precision while enabling scaled dimensions for improved transistor performance.
Solution Approach 2:
Different regions of the fin structure are assigned different liner qualities - the first liner provides baseline protection while the second liner provides enhanced protection at specific locations. This local quality differentiation allows the structure to maintain precise critical dimensions where needed while enabling overall scaling for better current control and short channel effect suppression.
2Reliability
If the two-dimensional width of the gate is increased to improve current control, then current control capability is improved, but device area increases
Solution Approach 1:
The invention transitions from two-dimensional gate width scaling to three-dimensional gate all around structures that surround the nanowire channel. This dimensional change allows current control to be achieved through the vertical and lateral enclosure of the gate rather than increasing the planar gate width, thereby improving current control capability without increasing device area.
Data Source
AI summary
A semiconductor device is provided as follows. A first fin is formed on a first region of a substrate, extending in a first direction. A second fin is formed on a second region of the substrate, extending in a second direction. A first dual liner is formed on a lateral surface of the first fin. The first dual liner includes a first liner and a second liner. The first liner is interposed between the second liner and the lateral surface of the first fin. A second dual liner is formed on a lateral surface of the second fin. The second dual liner includes a third liner and a fourth liner. The third liner is interposed between the fourth liner and the lateral surface of the second fin. An epitaxial layer surrounds a top portion of the second fin. The first liner and the third liner have different thicknesses.