Fin Edge and Major Cut Process for FinFET Overlay Error Reduction
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Solution Overview
Problem
The semiconductor industry faces challenges in manufacturing fin field effect transistors (FinFETs) and gate-all-around (GAA) FETs due to the complexity and cost associated with multi-cut processes, which can cause device degradation and introduce overlay errors between cut layers, while traditional methods are inefficient and costly.
Innovation Solution
A combined fin cut process is introduced, which separates the etching of edge and major structures using a single lithography process, reducing cycle time and cost, and minimizing over-etching effects by employing a fin-edge-cut and fin-major-cut process, thereby minimizing damage to adjacent fins and reducing overlay errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a multi-cut process is used to manufacture FinFETs or GAA FETs, then the fins can be removed with high precision, but the process complexity increases and manufacturing cost rises
Solution Approach 1:
The patent combines multiple fin cut operations into a single integrated process step. The method performs both edge-cut and major-cut of fins simultaneously using one lithography pattern and one etching operation, eliminating the need for separate lithography and etching steps that would otherwise be required for multi-cut processes. This merging reduces process complexity while maintaining the precision benefits of multiple cuts.
Solution Approach 2:
The patent segments the fin removal process into two functional zones within a single cut operation: an edge-cut region that removes fins at the perimeter and a major-cut region that removes fins in the interior. This segmentation is achieved through a specially designed lithography mask with different transparency regions, allowing selective fin removal in different areas during one etching process, thus maintaining high precision without increasing process steps.
2Manufacturing precision
If a multi-cut process is used, then fin removal can be achieved, but overlay errors between cut layers are introduced
Solution Approach 1:
The patent merges multiple cut operations into a single lithography-etch cycle, eliminating the need for sequential lithography steps that would require overlay alignment. By performing both edge-cut and major-cut in one process using a single lithography pattern, the method completely avoids overlay errors between cut layers while achieving the same fin removal results.
3Ease of manufacture
If traditional fin cut processes are used, then fins can be removed, but device degradation occurs due to over-etching
Solution Approach 1:
The patent applies local quality by creating different mask transparency regions tailored to specific spatial zones: a first transparency region for edge-cut areas and a second transparency region for major-cut areas. This allows the etching process to be selectively applied to different regions with appropriate etch depths and intensities, preventing over-etching in sensitive areas while efficiently removing fins in other areas, thus maintaining device integrity.
Solution Approach 2:
The patent performs preliminary action by using the lithography mask to pre-define the exact regions where fins should be removed before the etching process begins. The mask pattern is designed in advance to account for potential over-etching effects, creating a protective structure that limits etching to intended areas only, thereby preventing device degradation from excessive etching.
4Manufacturing precision
If multiple cutting steps are employed, then complete fin removal is achieved, but manufacturing cycle time increases
Solution Approach 1:
The patent merges multiple cutting steps into a single integrated process that accomplishes both edge-cut and major-cut operations simultaneously. By using one lithography exposure, one mask formation, and one etching step to achieve what would traditionally require multiple sequential operations, the method significantly reduces manufacturing cycle time while maintaining complete fin removal.
Data Source
AI summary
Manufacturing a semiconductor device includes forming a pad oxide layer on a semiconductor substrate. A hard mask layer is formed over the pad oxide layer. An anti-reflective layer (ARL) is formed over the hard mask layer. A first photoresist layer is formed over the ARL. The first photoresist layer is patterned and the hard mask layer and ARL are removed. Remaining portions of the first photoresist layer and the ARL are removed, and a patterned hard mask layer is formed. The pad oxide layer and the semiconductor substrate are etched to obtain a plurality of fins. A bottom layer is formed over and between the fins. A middle layer is formed over the bottom layer and a second photoresist layer is formed on the middle layer. The second photoresist layer is patterned to form an opening and a spacer is formed in an opening formed in the second photoresist layer.