Fin-End Isolation Structure for Uniform FinFET Gate And Epi Growth
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Solution Overview
Problem
The challenge in semiconductor manufacturing is to reduce the layout-dependent effect (LDE) on semiconductor fins caused by isolation structures, which affects the uniformity of fin profiles and epitaxial growth in ICs, necessitating advanced fabrication processes for FinFET or gate-all-around devices.
Innovation Solution
The proposed solution involves forming isolation features between semiconductor fins using a fin-end-cut process, where a spacer layer and inter-layer dielectric layer are used to create a self-aligned fin-cut trench, reducing stress and enhancing the uniformity of gate structures and epitaxial growth across the IC.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If isolation structures are formed around semiconductor fins, then electrical isolation between fins is achieved, but layout-dependent effects cause non-uniform fin profiles and non-uniform epitaxial growth
Solution Approach 1:
The patent applies local quality by forming isolation features only at specific locations (fin ends) rather than continuously around all fins. The fin-end-cut process creates localized isolation trenches at fin ends while leaving the fin sidewalls exposed, providing electrical isolation where needed without creating the continuous stress field that causes LDE. This selective localization of isolation structures eliminates the uniform stress that degrades fin profile uniformity and epitaxial growth across the entire IC.
2Reliability
If conventional isolation structures are used, then electrical isolation is provided, but stress is induced affecting gate structure uniformity and epitaxial growth uniformity
Solution Approach 1:
The patent segments the isolation structure into discrete fin-end-cut features rather than using continuous isolation structures around all fins. By cutting isolation trenches only at fin ends and filling them with dielectric material, the isolation function is segmented into localized units. This segmentation prevents the continuous stress field that would otherwise be imposed on the entire fin structure, thereby maintaining uniform epitaxial growth and gate structure formation across the IC while still providing electrical isolation at the segmented fin-end locations.
Data Source
AI summary
A method includes forming a fin protruding from a substrate, forming first and second gate structures across the fin, the first gate structure having a first gate sidewall facing the second gate structure, the second gate structure having a second gate sidewall facing the first gate structure, recessing a segment of the fin between the first and second gate sidewalls to form a trench, depositing a dielectric layer over the first and second gate sidewalls and within the trench, and depositing an inter-layer dielectric layer over the first and second gate structures and over the dielectric layer. A portion of the inter-layer dielectric layer is within the trench.