Fin End Plug Isolation Structure for 10 nm Fin Patterning Precision
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Solution Overview
Problem
The scaling of features in integrated circuits to the 10 nanometer node and smaller sizes faces challenges due to variability in conventional fabrication processes, limiting further extension into these technology nodes.
Innovation Solution
The implementation of advanced pitch quartering and merged fin pitch quartering approaches for patterning semiconductor fins, along with the use of three-layer trench isolation structures and fin end stressor dielectric plugs, to enhance the fabrication of integrated circuit structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used for scaling, then manufacturing simplicity is maintained, but manufacturing precision deteriorates due to variability at 10 nanometer node and smaller sizes
Solution Approach 1:
The patent applies pitch quartering by dividing the fin formation process into multiple patterning stages. First mandrels are formed, then spacers are deposited and patterned, followed by additional spacer formation to achieve quarter-pitch features. This segmentation enables manufacturing precision at 10nm node by breaking down the complex patterning into manageable steps, each with controlled precision requirements.
Solution Approach 2:
The patent implements merged fin pitch quartering where different regions of the semiconductor device receive different fin configurations. Some regions have merged fins while others have separated fins, allowing optimization of local electrical characteristics. This local quality approach addresses variability by tailoring fin structures to specific device requirements rather than applying uniform patterning across the entire wafer.
2Manufacturing precision
If advanced pitch quartering approaches are implemented, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent performs preliminary actions by forming sacrificial mandrels and spacers that define the final fin positions. The mandrels are formed first, then spacers are deposited conformally on the mandrels. These preliminary structures are later removed or transformed, but they have already established the precise geometric framework for the fins. This preliminary action reduces the complexity of the final patterning step while maintaining high precision.
Solution Approach 2:
The patent employs nested structures where spacers are formed around mandrels, then additional spacers are formed around the first spacers. Each patterning cycle nests new structures within or around previous structures, systematically reducing the pitch by factors of two or four. This nested approach organizes the complex multi-step process into a hierarchical sequence, making the overall device complexity manageable through modular repetition of the same patterning techniques.
Data Source
AI summary
Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first isolation structure over a first end of a fin. A gate structure is over the fin and is spaced apart from the first isolation structure along the direction. A second isolation structure is over a second end of the fin, the second end opposite the first end. The second isolation structure is spaced apart from the gate structure. The first isolation structure and the second isolation structure both comprise a first dielectric material laterally surrounding a recessed second dielectric material distinct from the first dielectric material. The recessed second dielectric material laterally surrounds at least a portion of a third dielectric material different from the first and second dielectric materials.