Fin-End Replacement Gate Structure for Poly Depletion Reduction
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Solution Overview
Problem
Metal-Oxide-Semiconductor (MOS) devices with polysilicon gate electrodes suffer from the poly depletion effect, which increases the effective gate dielectric thickness and makes it difficult to create an inversion layer, affecting the performance of Fin Field-Effect Transistors (FinFETs) and Gate-All-Around (GAA) transistors.
Innovation Solution
The formation of fin-end gate structures involves creating dummy gate stacks on protruding fins, removing the dummy gate electrodes while leaving the gate dielectric at the end portion unremoved to protect it from subsequent processes, and replacing the dummy gates with replacement gates to reduce the effective gate dielectric thickness and improve transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If polysilicon gate electrodes are used in MOS devices, then the work function can be adjusted to the band-edge of silicon, but the poly depletion effect increases the effective gate dielectric thickness and makes it difficult to create an inversion layer
Solution Approach 1:
The patent extracts and removes the polysilicon gate electrode material from the fin-end region, replacing it with a metal gate electrode. This extraction eliminates the source of the poly depletion effect (ionized donor sites in polysilicon) while maintaining the gate's essential function of controlling the inversion layer, thereby resolving the contradiction between work function adjustability and depletion effect harm.
Solution Approach 2:
The patent changes the material parameter of the gate electrode from polysilicon to metal, fundamentally altering the electrical properties. Metal gates do not exhibit the poly depletion effect because they lack ionized donor sites, thus reducing the effective gate dielectric thickness and improving inversion layer formation while maintaining appropriate work function through material selection.
2Reliability
If dummy gate stacks are formed and then removed to create trenches for replacement gates, then metal gates can be formed with band-edge work functions, but the process complexity increases with multiple steps including CMP
Solution Approach 1:
The patent applies local quality by differentiating the gate structure at fin-end regions from the main channel region. Instead of uniformly removing all dummy gates, the method selectively removes dummy gates only from fin-end regions while preserving them in the main channel, allowing localized metal gate formation without requiring full-wafer CMP processing, thus reducing overall process complexity.
Solution Approach 2:
The patent segments the gate formation process into distinct regions: fin-end regions receive metal replacement gates while main channel regions retain polysilicon dummy gates. This segmentation allows selective processing of problematic areas without subjecting the entire device to complex multi-step replacement gate procedures, simplifying the overall manufacturing process.
3Productivity
If the effective gate dielectric thickness is reduced to improve inversion layer formation, then transistor performance improves, but the gate dielectric structure becomes more critical and difficult to control
Solution Approach 1:
The patent employs composite gate dielectric structures combining different materials (e.g., silicon oxide, silicon nitride, or high-k materials) with varying dielectric constants. By using composite materials, the effective dielectric thickness can be reduced to improve transistor performance while maintaining adequate electrical control through the combined properties of multiple layers, thereby mitigating the difficulties associated with controlling thin single-layer dielectrics.
Data Source
AI summary
A method includes simultaneously forming a first dummy gate stack and a second dummy gate stack on a first portion and a second portion of a protruding fin, simultaneously removing a first gate electrode of the first dummy gate stack and a second gate electrode of the second dummy gate stack to form a first trench and a second trench, respectively, forming an etching mask, wherein the etching mask fills the first trench and the second trench, patterning the etching mask to remove the etching mask from the first trench, removing a first dummy gate dielectric of the first dummy gate stack, with the etching mask protecting a second dummy gate dielectric of the second dummy gate stack from being removed, and forming a first replacement gate stack and a second replacement gate stack in the first trench and the second trench, respectively.