Fin End Spacer Dummy Gate for FinFET Overlay Shift Protection
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Solution Overview
Problem
During the manufacturing of fin field effect transistors (FinFETs) and gate-all-around (GAA) FETs, overlay shift causes misalignment of structures, leading to the formation of narrow gaps that prevent the complete formation of protective layers, resulting in defects such as damaged or chemically altered source/drain epitaxial layers.
Innovation Solution
The implementation of a spacer dummy gate structure that forms a fin end spacer plug to fill the gap adjacent to the fin end, ensuring the source/drain epitaxial layer is protected from etching and chemical alteration by conformally forming a gate sidewall spacer layer and using a spacer dummy gate layer to preserve the epitaxial layer during processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional manufacturing processes are used without spacer dummy gate, then the manufacturing process is simpler, but overlay shift causes misalignment and narrow gaps that prevent complete formation of protective layers, resulting in damaged source/drain epitaxial layers
Solution Approach 1:
The spacer dummy gate structure is formed in advance before the source/drain epitaxial layer formation. This preliminary structure serves as a protective placeholder that ensures proper spacing and prevents misalignment issues during subsequent processing steps, thereby protecting the epitaxial layer from damage while maintaining manufacturing feasibility
Solution Approach 2:
The spacer dummy gate acts as an intermediary structure between the fin structure and the source/drain region. It provides a physical barrier and spacing reference that prevents direct contact between misaligned structures, thereby protecting the source/drain epitaxial layer from etching damage and chemical alteration during processing
2Reliability
If no fin end spacer plug is formed, then the manufacturing process is simpler, but narrow gaps prevent complete formation of gate sidewall spacer layers, leading to unprotected epitaxial layers
Solution Approach 1:
The fin end spacer plug is formed preliminarily in the narrow gap region before the gate sidewall spacer layer formation. This preliminary spacer plug ensures that the subsequent gate sidewall spacer layer can be completely formed without being interrupted by the narrow gap, thereby ensuring complete protection of the source/drain epitaxial layer
Solution Approach 2:
The problematic narrow gap region is effectively removed or filled by forming the fin end spacer plug. This extraction of the gap problem allows the gate sidewall spacer layer to be formed continuously and completely, ensuring full protection of the epitaxial layer without compromising manufacturing feasibility
Data Source
AI summary
A semiconductor device includes a plurality of fins on a substrate. A fin liner is formed on an end surface of each of the plurality of fins. An insulating layer is formed on the plurality of fins. A plurality of polycrystalline silicon layers are formed on the insulating layer. A source/drain epitaxial layer is formed in a source/drain space in each of the plurality of fins. One of the polycrystalline silicon layers is formed on a region spaced-apart from the fins.