Fin Structure Etch-Back for Flat Buried Word Line Profiles
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Solution Overview
Problem
The etch-back process for forming buried word lines in semiconductor structures often results in variations in height due to poor selectivity, leading to rounded fin structures that negatively impact electrical performance.
Innovation Solution
A method involving a first etch-back process to form a fin structure with a protruding portion, followed by a second etch-back process using a hard mask and plasma etching with specific power and frequency settings to achieve a fin structure with a substantially flat top surface, preventing rounding and enhancing electrical properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single etch-back process is used to form buried word lines, then the fabrication process is simple, but the heights of materials vary due to poor etching selectivity
Solution Approach 1:
The single etch-back process is divided into two sequential etch-back processes. The first etch-back process removes a first portion of the dielectric material, and the second etch-back process removes a second portion. This segmentation allows each process to be optimized for specific removal depths and selectivities, improving overall height uniformity while maintaining fabrication simplicity.
Solution Approach 2:
The first etch-back process is performed as a preliminary action before the second etch-back process. By pre-removing a first portion of the dielectric material with controlled selectivity, the subsequent second etch-back process can focus on achieving the final precise height uniformity, thereby resolving the contradiction between process simplicity and manufacturing precision.
2Ease of manufacture
If etch-back process is used for forming buried word lines, then space is created for conductive material deposition, but fin structures become rounded due to height variations
Solution Approach 1:
The etch-back process is segmented into two stages: first creating the necessary space for conductive material deposition, then performing a second etch-back to precisely control fin structure heights. This ensures both the deposition capability and the flat fin profiles are achieved without compromising either requirement.
Solution Approach 2:
The etching selectivity parameters are changed between the two etch-back processes. The first process uses selectivity optimized for creating deposition space, while the second process uses selectivity optimized for maintaining fin structure profiles. This parameter change allows both contradictory requirements to be satisfied.
3Ease of manufacture
If conventional etch-back process is used, then fabrication is straightforward, but electrical performance deteriorates due to rounded fin structures
Solution Approach 1:
The fabrication process is segmented into two etch-back steps, where the first step maintains straightforward fabrication by creating initial space, and the second step improves electrical performance by precisely controlling fin structure heights and preventing rounding. This segmentation resolves the contradiction between ease of manufacture and reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method improves the profile of fin structures, contributing to better electrical properties of buried word lines by maintaining a flat top surface and adjusting etching selectivity, thus addressing the issue of height variations and rounded fins.
Implementation Method 1
performing a second etching process to remove a portion of the dielectric material and the protruding portion of the second fin structure to form a third fin structure
Data Source
AI summary
The present disclosure provides a semiconductor structure having a fin structure. The semiconductor includes a substrate defined with an active region. A first gate structure is disposed in the active region and includes a dielectric material. A second gate structure is disposed in the active region and includes the dielectric material. A fin structure having a first top surface is arranged to alternate with the first gate structure and the second gate structure. The first gate structure has a second top surface and the second gate structure has a third top surface. The second top surface and the third top surface are lower than the first top surface.