Fin Etching Using Sequential Masks for High Aspect Ratio

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Solution Overview

Problem

Existing semiconductor device fabrication methods struggle to create fins with high aspect ratios, as single etching processes often result in erosion of hard masks, making it difficult to achieve narrow fin widths due to lateral etching effects.

Innovation Solution

A method involving separate and sequential etching processes using different masks, where the first mask forms a first side wall and the second mask forms a second side wall, allowing for the formation of fins with high aspect ratios by preventing rapid erosion of the masks and enabling precise control over fin width.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If a single etching process is used to form fins, then the fabrication process is simple and fast, but the hard mask erodes rapidly due to lateral etching effects, making it difficult to achieve narrow fin widths and high aspect ratios

Engineering Contradiction:
Improvefin width precisionVSAvoidetching process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The single etching process is divided into multiple sequential etching steps, each with its own mask and parameters. The first etching forms initial fin structures, while subsequent etchings refine the fin width and create high aspect ratios. This segmentation allows precise control over fin dimensions without mask erosion, as each step uses optimized parameters for its specific purpose.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The first mask and first etching step perform preliminary actions by forming initial fin structures with controlled widths. This preliminary formation creates a foundation that protects against subsequent mask erosion, as the fin structures are already established before the second etching begins. The preliminary action enables the second etching to focus solely on refining dimensions without compromising mask integrity.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If the gate length is increased to improve current control capability, then current control improves, but the device area increases and scaling becomes difficult

Engineering Contradiction:
Improvecurrent control capabilityVSAvoiddevice area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The invention transitions from planar (2D) channel structures to three-dimensional (3D) fin structures with high aspect ratios. By etching deep, narrow fins into the substrate, the channel gains vertical dimension, providing enhanced gate control over the channel current without increasing the horizontal device footprint. The multi-step etching process enables these high aspect ratio fins, where the channel height (vertical dimension) provides the control mechanism rather than horizontal gate length extension.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Reliability

If conventional etching processes are used, then the process is simple and fast, but short channel effects occur where electric potential of the channel region is affected by drain voltage

Engineering Contradiction:
Improveshort channel effect suppressionVSAvoidfabrication productivity
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The etching process is segmented into multiple steps with different parameters and masks, allowing precise control over fin geometry. The first etching creates initial fin structures, while the second etching refines the fin width and enhances the aspect ratio. This segmented approach produces fins with dimensions that effectively suppress short channel effects by providing sufficient gate control over the channel, while the systematic process design maintains reasonable fabrication productivity through efficient process sequencing.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS9634093B2Method for fabricating semiconductor device
Publication Date: 2017.04.25 SAMSUNG ELECTRONICS CO LTD
  • US9634093B2 patent drawing
  • US9634093B2 patent drawing
  • US9634093B2 patent drawing

AI summary

A method for fabricating a semiconductor device includes forming a first mask on a substrate, forming a first side wall of a fin by performing a first etching of the substrate using the first mask, forming a second mask on the substrate, the second mask being different from the first mask, and forming a second side wall of the fin by performing a second etching of the substrate using the second mask.