Fin Structure Etching With Annealing to Reduce Sidewall Damage
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Solution Overview
Problem
The challenge in semiconductor manufacturing lies in achieving defect-free and damage-free fin structures during plasma etching processes for FinFETs, particularly at sub-10-15 nm technology nodes, where precise critical dimension control is crucial.
Innovation Solution
A pulsed-bias etching process is employed using a plasma etching apparatus with controlled DC and RF power, combined with annealing operations to minimize sidewall damage and defects, followed by meticulous cleaning and re-crystallization of the fin structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If plasma etching is used to form fin structures, then high etch depth and precision are achieved, but sidewall damage and defects are introduced
Solution Approach 1:
The patent employs pulsed bias conditions during plasma etching, where the bias voltage is applied in periodic pulses rather than continuously. This allows alternating phases of ion bombardment (for etching) and reduced bombardment (for damage reduction), achieving both deep etching and minimized sidewall damage through time-modulated control of the plasma process
Solution Approach 2:
The patent modifies plasma process parameters including bias voltage, RF power, and gas composition during the etching process. By dynamically adjusting these parameters, the process optimizes the balance between ion bombardment intensity (needed for deep etching) and sidewall damage accumulation, achieving high precision while minimizing harmful effects
2Productivity
If continuous ion bombardment is applied during etching, then etching speed increases, but sidewall damage accumulates
Solution Approach 1:
The pulsed bias scheme creates periodic cycles of high ion bombardment (etching phase) followed by reduced bombardment (recovery phase). This temporal modulation maintains high average etching speed while periodically reducing damage accumulation, resolving the contradiction between productivity and harmful effects
Solution Approach 2:
The patent converts the potentially harmful continuous ion bombardment into a beneficial periodic process where ion bombardment phases create the desired etching, while the intervening low-bias phases allow for damage mitigation. The harmful ion bombardment is thus transformed into a controlled, beneficial process through periodic application
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures vertical ion bombardment minimizes sidewall damage, maintains fin structure integrity, and reduces defects, enabling high etch depth and precision, thus supporting the formation of FinFETs with improved performance and reliability.
Implementation Method 1
a pulsed-bias etching process is employed using a plasma etching apparatus
Implementation Method 2
Vertical ion bombardment minimizes sidewall damage
Implementation Method 3
an annealing operation is performed on the fin structure... the annealing operation eliminates the damaged area
Data Source
AI summary
In a method of manufacturing a semiconductor device, a fin structure is formed by patterning a semiconductor layer, and an annealing operation is performed on the fin structure. In the patterning of the semiconductor layer, a damaged area is formed on a sidewall of the fin structure, and the annealing operation eliminates the damaged area.