High-Aspect-Ratio Fin Etching for Uniform Nested and Isolated Fins
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Solution Overview
Problem
As microprocessors become faster and smaller, maintaining uniform widths and rectangular cross-sections of high aspect ratio fin-based transistor devices becomes increasingly difficult due to micro loading effects, which cause variations in etching rates and resulting metrics like leakage current and threshold voltage between nested and isolated fins.
Innovation Solution
The use of multiple substrate etching processes with specific etching chemistries, such as hydrogen-rich and chlorine-based plasmas, to achieve uniform fin widths across nested and isolated fins, along with a hard mask patterning process to control the etching and passivation of sidewalls, ensuring consistent dimensions and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single etching process is used to form nested fins and isolated fins, then the manufacturing process is simple, but the fin widths become non-uniform due to micro loading effects
Solution Approach 1:
The patent divides the etching process into multiple sequential steps: a first etching process forms initial fins, followed by a second etching process that selectively removes material between fins to create nested structures. This segmentation allows different etching conditions to be applied to different fin types, achieving uniform widths despite different final configurations.
Solution Approach 2:
The first etching process performs preliminary fin formation with controlled dimensions before the nested structure creation. By pre-establishing uniform fin widths in the initial process, the patent ensures that subsequent processing maintains width uniformity while creating the nested configuration.
2Adaptability or versatility
If the pitch between fin based structures is non-uniform, then the circuit design flexibility is improved, but the micro loading effect becomes more significant causing different etch bias
Solution Approach 1:
The patent applies different etching conditions to different local regions: isolated fins receive one etching regime while nested fins receive another. This local quality approach allows each fin type to be optimized independently, achieving uniform widths despite different pitches and configurations.
Solution Approach 2:
The patent changes etching parameters (such as gas composition, power, pressure) between the first and second etching processes, and between isolated and nested fin processing. By adjusting these parameters, the patent compensates for micro loading effects and achieves consistent fin widths across different pitch configurations.
3Reliability
If the aspect ratio of transistor devices is increased, then the device performance is improved, but the difficulty of maintaining uniform fin widths increases
Solution Approach 1:
The patent uses periodic etching cycles with alternating chemistry types (e.g., fluorine-based followed by chlorine-based). This periodic action allows controlled material removal that maintains sidewall integrity while achieving the required etch depth, preserving width uniformity in high aspect ratio structures.
Solution Approach 2:
The patent employs composite etching chemistries that combine different gas components (fluorine, chlorine, oxygen, nitrogen) in specific ratios. This composite approach provides both vertical etch rate and sidewall protection, enabling uniform fin width maintenance even as aspect ratios increase.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the production of high aspect ratio fin-based semiconductor devices with uniform metrics, enabling the use of nested and isolated fins in circuitry with consistent performance and reduced micro loading effects, thereby improving device reliability and efficiency.
Implementation Method 1
The use of multiple substrate etching processes with specific etching chemistries, such as hydrogen-rich and chlorine-based plasmas
Implementation Method 2
a first substrate etching process may result in the nested fins having a smaller width than the width of the isolated fins
Implementation Method 3
a second substrate etching process may be included to equalize the widths of the isolated fins and the nested fins
Implementation Method 4
a hard mask patterning process may be included that transfers the fin shapes formed in a dummy hard mask into a hard mask layer
Data Source
Figure 1
Figure 2A~2B
Figure 2C~2D
AI summary
Embodiments of the invention describe semiconductor devices with high aspect ratio fins and methods for forming such devices. According to an embodiment, the semiconductor device comprises one or more nested fins and one or more isolated fins. According to an embodiment, a patterned hard mask comprising one or more isolated features and one or more nested features is formed with a hard mask etching process. A first substrate etching process forms isolated and nested fins in the substrate by transferring the pattern of the nested and isolated features of the hard mask into the substrate to a first depth. A second etching process is used to etch through the substrate to a second depth. According to embodiments of the invention, the first etching process utilizes an etching chemistry comprising HBr, O2 and CF4, and the second etching process utilizes an etching chemistry comprising Cl2, Ar, and CH4.