Fin Fabrication Process Using Selective Dummy Fin Removal

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Solution Overview

Problem

Current FinFET semiconductor fabrication techniques face challenges in minimizing fin defects during the removal process, particularly in achieving precise control over the number of fins per transistor in multiple cells, which affects the performance and density of integrated circuits.

Innovation Solution

The method involves strategically depositing first and second fin spacers with different materials and using hard masks to selectively remove dummy fins without damaging desired fins, allowing for simultaneous fabrication of various fin cell configurations, such as 1, 2, 3, 4, or 5 fins per transistor by carefully positioning the edges of protective mask layers to protect the desired spacers during patterning operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If dummy fins are removed to achieve variable fin configurations, then fin cell versatility is improved, but fin defects increase due to damage to desired fins

Engineering Contradiction:
Improvefin cell configurationVSAvoidfin defect
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent divides the fin structure into desired fins and dummy fins that can be selectively removed. By segmenting the fin configurations, the process enables variable fin cell designs (1-fin, 2-fin, 3-fin, 4-fin, or 5-fin cells) while isolating the removal process to only dummy fins through protective mask layers, preventing damage to desired fins and reducing fin defects

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies protective mask layers to desired fins before the dummy fin removal process. This preliminary protective action ensures that when dummy fins are removed to achieve variable configurations, the desired fins are already protected and cannot be damaged, thus eliminating fin defects while maintaining configuration versatility

Inventive Principle:
Principle #10Preliminary action

2Productivity

If multiple fin cell configurations are fabricated simultaneously, then chip area usage is improved, but manufacturing complexity increases

Engineering Contradiction:
Improvechip area usageVSAvoidfabrication process
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent creates a universal fin fabrication process that can simultaneously produce multiple fin cell configurations (1-fin, 2-fin, 3-fin, 4-fin, or 5-fin cells) using the same base process steps. The protective mask layer strategy enables this multi-functionality by allowing selective dummy fin removal across different cell types in a single process flow, maximizing chip area usage without proportionally increasing manufacturing complexity

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent applies different protective mask layer strategies to different regions of the wafer to achieve local quality variations. By positioning protective mask edges at specific locations relative to desired and dummy fins in different cell configurations, the process selectively protects desired fins while enabling dummy fin removal, allowing simultaneous fabrication of diverse fin cell types with locally optimized outcomes

Inventive Principle:
Principle #3Local quality

3Area of stationary object

If protective mask edges are positioned close to desired fins for compact design, then header area is improved, but risk of fin damage increases

Engineering Contradiction:
Improveheader areaVSAvoidfin damage risk
Core Design Contradiction:
Area of stationary objectVSObject-affected harmful factors

Solution Approach 1:

The patent introduces protective mask layers as intermediary protective elements between the dummy fin removal process and the desired fins. These mask layers can be positioned with edges close to desired fins to minimize header area, while still providing adequate protection through their material properties and positioning strategy, thus reducing fin damage risk even in compact designs

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS9679994B1High fin cut fabrication process
Publication Date: 2017.06.13 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US9679994B1 patent drawing
  • US9679994B1 patent drawing
  • US9679994B1 patent drawing

AI summary

A method of forming fins on a substrate is provided. The method comprises depositing first fin spacers comprising first fin spacer material and second fin spacers comprising second fin spacer material on a plurality of locations on a substrate having a hard mask above the substrate's semiconductor material, wherein the first fin spacers comprise desired first fin spacers and dummy first fin spacers and the second fin spacers comprise desired second fin spacers and dummy second fin spacers. The method further comprises forming fins on the substrate under the first fin spacers and the second fin spacers. The fins comprise a plurality of dummy fins and a plurality of desired fins. The dummy fins comprise a plurality of dummy first fins formed under the dummy first fin spacers and a plurality of dummy second fins formed under the dummy second fin spacers. The method further comprises removing the dummy first fin spacers separately from removing the dummy second fin spacers, removing the dummy second fin spacers, and removing the dummy fins without damaging the desired fins.