Fin Feature Formation via Mandrel and Spacer Etching
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Solution Overview
Problem
Existing methods for fabricating semiconductor devices face challenges in forming small critical dimension features, such as fins, with high precision and efficiency, particularly in scaling down processes that increase complexity and require improved manufacturing techniques.
Innovation Solution
The method involves depositing a dielectric layer and a hard mask over a substrate, forming mandrel features and spacers, selectively removing the mandrel, and etching to create fin trenches, allowing for the formation of semiconductor features with controlled width and height, thereby relaxing lithography constraints and reducing thermal budget impacts on fin features.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithography methods are used to form small critical dimension features, then manufacturing complexity increases, but manufacturing precision deteriorates
Solution Approach 1:
The process segments fin formation into distinct stages: mandrel formation, spacer deposition, selective mandrel removal, and fin trench etching. This segmentation allows each step to be optimized independently, achieving precise fin dimension control without proportionally increasing overall process complexity
Solution Approach 2:
Mandrel features and spacers are formed in advance before the actual fin trench etching. This preliminary action establishes precise geometric templates that guide subsequent etching, ensuring accurate fin feature dimensions while simplifying the critical etching step
2Manufacturing precision
If thermal budget is reduced to protect fin features, then manufacturing precision improves, but productivity decreases
Solution Approach 1:
Isolation regions are formed before fin features undergo stress-inducing processes. This preliminary action protects fin features from thermal damage during subsequent fabrication steps, maintaining manufacturing precision without requiring reduced thermal budget that would slow down overall production
Solution Approach 2:
The isolation region acts as a protective barrier that preemptively prevents thermal damage to fin features. This preliminary anti-action allows normal thermal processing conditions to be maintained, preserving both fin feature quality and fabrication efficiency
3Area of moving object
If fin feature size is reduced, then area of moving object decreases, but manufacturing precision becomes more difficult to maintain
Solution Approach 1:
Spacer material serves as an intermediary that transfers the precisely controlled mandrel dimensions to the final fin feature dimensions. This intermediary mechanism enables accurate dimensional control even as fin feature size decreases, since the spacer thickness can be precisely controlled through deposition processes
Solution Approach 2:
The process controls fin feature dimensions by transitioning from lateral control (mandrel width) to vertical control (spacer thickness). This dimensional change allows precise control of small fin features, as thin film deposition provides superior thickness control compared to lithographic width control
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the precise formation of fin features with reduced stress relaxation and maintained strain levels, improving control over fin feature dimensions and isolation region quality while simplifying the process and avoiding adverse thermal budgets.
Implementation Method 1
depositing a dielectric layer and a hard mask
Implementation Method 2
depositing a dielectric layer and a hard mask
Implementation Method 3
etching to create fin trenches
Implementation Method 4
etching to create fin trenches
Data Source
AI summary
A method of fabricating a semiconductor device is disclosed. The method includes forming a dielectric layer over a substrate, forming a hard mask (HM) layer over the dielectric layer, forming a fin trench through the HM layer and the dielectric layer and extending down to the substrate, forming a semiconductor feature in the fin trench and removing the HM layer to expose an upper portion of the semiconductor feature to form fin features.