Fin-Structured Ferroelectric Memory for Higher-Density FTJ Reads
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Solution Overview
Problem
Ferroelectric tunnel junction (FTJ) devices face challenges in scaling size and increasing density due to reduced charge carriers and tunneling current density, which decreases memory window and read operation speed and accuracy.
Innovation Solution
The implementation of a ferroelectric tunnel junction device with a ferroelectric layer disposed along the sidewalls and upper surface of a fin structure, increasing the overlap area between the conductive structure and the semiconductor layer, thereby enhancing tunneling current density and charge carrier accumulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the FTJ device size is scaled down to increase density, then device density is improved, but tunneling current density and charge carrier number decrease
Solution Approach 1:
The patent transitions from a planar FTJ structure to a vertical fin-based structure, utilizing the third dimension (vertical height) to increase the effective tunneling area. The fin structure extends vertically from the substrate, providing additional surface area for the ferroelectric layer and conductive structure to interact, thereby maintaining sufficient tunneling current density even as the lateral device footprint is reduced to increase density.
2Quantity of substance
If the FTJ device size is scaled down to increase density, then device density is improved, but memory window decreases
Solution Approach 1:
By extending the ferroelectric layer vertically along the fin structure, the patent increases the total volume and effective area of the ferroelectric material without increasing the lateral device size. This dimensional transition allows sufficient charge carrier accumulation to maintain the memory window while achieving higher device density through reduced lateral footprint.
3Quantity of substance
If the FTJ device size is scaled down to increase density, then device density is improved, but read operation speed and accuracy decrease
Solution Approach 1:
The vertical fin structure provides increased surface area for charge carrier accumulation and tunneling events. This additional area in the vertical dimension compensates for the reduced lateral dimensions, maintaining sufficient tunneling current density and charge carrier numbers required for fast and accurate read operations, even as device density is increased through scaling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration increases the memory window and improves the speed and accuracy of read operations in FTJ devices by increasing the number of charge carriers and tunneling current density.
Implementation Method 1
a ferroelectric layer between the conductive structure and the semiconductor layer
Implementation Method 2
By applying a first voltage to the conductive structure, the polarization of the ferroelectric layer may be in a first direction such that the ferroelectric layer has a first resistance indicating a first data state
Data Source
AI summary
Various embodiments of the present disclosure are directed towards an integrated chip including a fin structure extending vertically from a semiconductor substrate. The fin structure continuously extends laterally along a first direction. A ferroelectric memory stack overlies the fin structure and continuously laterally extends along a second direction that is substantially perpendicular to the first direction. The ferroelectric memory stack includes an upper electrode overlying a ferroelectric layer. The ferroelectric layer extends along opposing sidewalls and an upper surface of the fin structure.