Fin FET Sidewall Buffer Pattern for Stress Relief
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Solution Overview
Problem
Conventional fin FETs face issues with sidewall damage and defects during manufacturing, leading to degraded electrical characteristics and increased current leakage due to the etching process, which affects the performance and integration density of semiconductor devices.
Innovation Solution
A fin FET design that incorporates a buffer pattern with etching selectivity between the first and second silicon nitride patterns, along with a device isolation layer, to mitigate sidewall defects and maintain the original shape of the capping layer, thereby alleviating internal stresses and improving electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the etching process is used to form the fin structure, then the fin shape is defined, but sidewall damage and defects occur leading to degraded electrical characteristics
Solution Approach 1:
A buffer oxide layer is formed on the sidewalls of the fin structure before the main etching process. This buffer layer acts as a protective cushion that prevents direct contact between the etchant and the critical sidewall regions, thereby preventing sidewall damage and defects while still allowing the etching process to define the fin shape accurately.
Solution Approach 2:
The buffer oxide layer serves as an intermediary layer between the etching process and the fin sidewalls. It mediates the interaction by providing a sacrificial layer that can be selectively removed or retained, protecting the underlying silicon sidewalls from etching damage while allowing precise fin formation.
2Productivity
If the gate length is scaled down to increase integration density, then more devices can be integrated, but short channel effects degrade device performance
Solution Approach 1:
The invention transitions from conventional planar gating to three-dimensional fin FET structure with gates wrapping around the fin from multiple directions. This dimensional change provides enhanced gate control over the channel region, effectively suppressing short channel effects even when the gate length is scaled down to increase integration density.
Solution Approach 2:
The gate structure is segmented into multiple gates positioned at different locations (front gate, back gate, and sidewall gates) that independently control different portions of the channel. This segmentation allows for distributed control of the channel, improving overall gate effectiveness and reducing short channel effects.
3Ease of manufacture
If the capping layer shape is altered during processing, then manufacturing flexibility is improved, but internal stresses increase leading to device defects
Solution Approach 1:
The buffer oxide layer is formed beforehand on the fin sidewalls to cushion and protect against shape alterations of the capping layer during processing. Even when the capping layer shape changes due to etching or other processing steps, the buffer layer prevents these changes from translating into harmful internal stresses in the underlying fin structure.
Solution Approach 2:
The buffer oxide layer acts as an intermediary that decouples the capping layer from the fin structure. This allows the capping layer to undergo shape alterations during manufacturing without directly transmitting stresses to the fin, while still maintaining proper device function.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution effectively prevents sidewall damage and maintains the original shape of the capping layer, reducing current leakage and enhancing the operational performance and integration density of fin FETs by alleviating internal stresses and improving gate control.
Implementation Method 1
A buffer pattern is provided between the first oxide pattern and the second silicon nitride pattern, and the buffer pattern has an etching selectivity with respect to the second silicon nitride pattern
Implementation Method 2
A device isolation layer is provided on the second silicon nitride pattern, so that a top surface of the device isolation layer is substantially coplanar with top surfaces of the oxide pattern and the second silicon nitride pattern
Data Source
AI summary
In a fin field effect transistor (FET), an active pattern protrudes in a vertical direction from a substrate and extends across the substrate in a first horizontal direction. A first silicon nitride pattern is formed on the active pattern, and a first oxide pattern and a second silicon nitride pattern are sequentially formed on the substrate and on a sidewall of a lower portion of the active pattern. A device isolation layer is formed on the second silicon nitride pattern, and a top surface of the device isolation layer is coplanar with top surfaces of the oxide pattern and the second silicon nitride pattern. A buffer pattern having an etching selectivity with respect to the second silicon nitride pattern is formed between the first oxide pattern and the second silicon nitride pattern. Internal stresses that can be generated in sidewalls of the active pattern are sufficiently released and an original shape of the first silicon nitride pattern remains unchanged, thereby improving electrical characteristics of the fin FET.