Fin FET Etch Stop Layer for Uniform Stress and Mobility
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Solution Overview
Problem
Semiconductor devices face challenges in achieving improved mobility characteristics and reducing dispersion of device characteristics, particularly in fin field effect transistors, due to complex structures and etching processes that can lead to non-uniformity and characteristic variations.
Innovation Solution
The solution involves a fin field effect transistor design with specific layer structures, including a buffer pattern, channel pattern, and etch stop pattern, where the etch stop pattern has higher etch resistivity than the buffer pattern, and the channel pattern includes materials like germanium or III-V group compound semiconductors, to generate tensile or compressive stress and improve carrier mobility. The method involves forming recess regions and re-growing semiconductor layers with an etch stop layer to ensure uniform thickness and reduce characteristic dispersion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If complex structures and etching processes are used to achieve high integration, then device functionality is improved, but manufacturing precision deteriorates due to non-uniformity and characteristic variations
Solution Approach 1:
An etch stop layer is introduced as an intermediary between the buffer layer and the active device structure. This etch stop layer serves as a reference plane that enables precise depth control during etching processes, ensuring uniform etching depth across different regions and devices, thereby resolving the contradiction between complex device functionality and manufacturing precision.
Solution Approach 2:
The patent utilizes changes in material properties (etch selectivity) by introducing layers with different etch rates. The etch stop layer has distinct etching characteristics compared to surrounding layers, allowing for precise control of etching depth and maintaining manufacturing precision even as device complexity increases.
2Reliability
If stress is applied to improve carrier mobility, then device performance is improved, but characteristic dispersion increases due to non-uniform stress distribution
Solution Approach 1:
The etch stop layer acts as a mediator that ensures uniform stress distribution across the device structure. By providing a stable reference plane and controlling the depth of subsequent layers, it enables consistent stress application in the channel region, improving carrier mobility while reducing characteristic dispersion.
Solution Approach 2:
The device structure is segmented into distinct functional layers with the etch stop layer providing a clear boundary. This segmentation allows for independent optimization of stress characteristics in the active region while maintaining overall structural uniformity, thereby improving reliability without increasing dispersion.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances carrier mobility and reduces characteristic dispersion in semiconductor devices by providing uniform stress in channel regions and ensuring uniform layer thickness, facilitating the formation of high-performance CMOS structures with improved operational characteristics.
Implementation Method 1
The etch stop pattern may include a material having an etch resistivity greater than that of the buffer pattern
Implementation Method 2
the channel pattern includes materials like germanium or III-V group compound semiconductors, to generate tensile or compressive stress and improve carrier mobility
Data Source
AI summary
A fin field effect transistor includes a first fin structure and a second fin structures both protruding from a substrate, first and second gate electrodes on the first and second fin structures, respectively, and a gate dielectric layer between each of the first and second fin structures and the first and second gate electrodes, respectively. Each of the first and second fin structures includes a buffer pattern on the substrate, a channel pattern on the buffer pattern, and an etch stop pattern provided between the channel pattern and the substrate. The etch stop pattern includes a material having an etch resistivity greater than that of the buffer pattern.