Fin FET Gate Electrode Wiring Path Integration
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Solution Overview
Problem
In planar FET structures, the gate electrode does not extend to the tap regions, leading to wire congestion and increased area due to the need for wires above the gate electrode to connect semiconductor elements.
Innovation Solution
The use of fins on the substrate with electrodes connected to them, allowing for alternative wiring configurations that reduce wire congestion and area by using the electrodes as signal transmission paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wires in the layer above the gate electrode are used to connect semiconductor elements straddling taps, then connectivity is achieved, but wire track availability is reduced leading to wire congestion and increased device area
Solution Approach 1:
The gate electrode is extended into the tap region to serve dual functions: maintaining its original gate control function over the channel region and simultaneously providing a wiring path for connecting semiconductor elements. This multi-functionality eliminates the need for separate wiring layers in the tap region, reducing wire congestion and device area while maintaining connectivity.
Solution Approach 2:
The gate electrode is extended in the lateral direction into the tap region, utilizing the horizontal dimension for wiring purposes. This dimensional extension allows the gate electrode to function as both a control element and a interconnect, thereby reducing the need for additional vertical wiring layers and decreasing overall device area.
2Reliability
If wires in the layer above the gate electrode are used to connect semiconductor elements straddling taps, then connectivity is achieved, but wire track availability is reduced leading to wire congestion
Solution Approach 1:
The gate electrode is extended into the tap region to serve dual functions: maintaining its original gate control function over the channel region and simultaneously providing a wiring path for connecting semiconductor elements. This multi-functionality eliminates the need for separate wiring layers in the tap region, reducing wire congestion and device area while maintaining connectivity.
Solution Approach 2:
The gate electrode structure serves itself by extending into the tap region to provide its own wiring function. This self-service approach allows the gate electrode to fulfill both its control function and interconnect function, eliminating the need for additional dedicated wiring structures and reducing overall device complexity.
Data Source
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AI summary
A semiconductor device (1) according to an embodiment includes: a semiconductor substrate; a first well region (15) formed on the semiconductor substrate; a first fin (11) integrally formed of the semiconductor substrate on the first well region and extended in a first direction in a plan view; a first electrode (12a) formed on the first fin via a first gate insulating film (17), and extended in a second direction crossing the first direction in the plan view; a tap region (20) formed on the semiconductor substrate adjacent to the first well region in the second direction, and supplying a first potential (VSS) to the first well region; a second fin (21) integrally formed of the semiconductor substrate on the tap region and extended in the first direction in the plan view; and a first wiring layer (23a) formed on the second fin in a portion overlapping the tap region in the plan view, extended in the second direction, and supplying the first potential to the first well region via the second fin and the tap region. The first electrode is formed on the second fin via a second gate insulating film (17). The semiconductor device further comprises: a second well region formed on the semiconductor substrate on an opposite side of the first well region to the tap region in the second direction, and a third fin integrally formed of the semiconductor substrate on the second well region and extended in the first direction in the plan view, wherein the first electrode is formed on the third fin via a third insulating film in the plan view.