Fin FET Memory System Using Silicon-Rich Nitride Charge Trapping
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Solution Overview
Problem
Current non-volatile memory technologies face challenges in reducing memory cell size due to the short channel effect and reduced drive current, leading to increased programming time and decreased data retention, particularly in floating gate and nitride-based Flash memories.
Innovation Solution
A memory system is developed using Fin FET technology with a silicon-rich nitride charge-storage layer, isolated by insulator layers, to form a self-aligned SONOS Fin FET structure, which enhances charge trapping and data retention while maintaining scalable cell sizes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the channel length is shrunk to reduce cell size, then memory density is improved, but short channel effect degrades cell performance
Solution Approach 1:
The patent transitions from planar 2D channel structure to 3D vertical fin structure. The fin extends vertically from the substrate, creating a three-dimensional channel that provides better gate control over the current flow path, thereby mitigating short channel effects while maintaining scaled dimensions.
Solution Approach 2:
The patent employs a composite material structure with silicon-rich nitride layer combined with insulator layers forming a SONOS (Silicon-Oxide-Nitride-Oxide-Semiconductor) stack. This composite structure enables effective charge trapping while maintaining electrical isolation, resolving the performance degradation issue.
2Area of moving object
If the channel width is shrunk to reduce cell size, then memory density is improved, but drive current is reduced
Solution Approach 1:
The vertical fin structure exploits the third dimension (vertical direction) to provide additional channel width through the fin height, compensating for the reduced lateral channel width. This allows the gate to control a larger effective channel area without increasing the planar footprint, thereby maintaining drive current while achieving cell size reduction.
3Ease of manufacture
If floating gate architecture is used, then implementation simplicity is achieved, but programming time increases and data retention decreases with new semiconductor processes
Solution Approach 1:
The patent extracts the charge storage function from the floating gate structure and places it in a dedicated silicon-rich nitride charge trapping layer. This separation allows the gate structure to be optimized for control while the nitride layer specifically handles charge storage, improving programming speed and retention without sacrificing manufacturing simplicity.
Solution Approach 2:
The patent changes the material parameter by using silicon-rich nitride instead of conventional oxide or simple nitride layers. The silicon content in the nitride layer is specifically optimized to enhance charge trapping efficiency and data retention characteristics, addressing the retention issues with new semiconductor processes.
4Adaptability or versatility
If charge trapping architecture is used, then scalability to new semiconductor processes is improved, but programming performance is poor
Solution Approach 1:
The patent optimizes the silicon content parameter in the nitride layer to achieve the right balance between charge trapping efficiency and programming speed. The silicon-rich composition enhances charge trapping capability for good retention while the controlled silicon content prevents excessive trapping that would slow programming, thus improving overall programming performance.
Solution Approach 2:
The SONOS composite structure combines multiple materials (oxide, nitride, semiconductor) with optimized thicknesses and compositions. The silicon-rich nitride layer works synergistically with the surrounding oxide layers to provide both fast programming through efficient charge injection and good retention through effective charge trapping.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly improves programming performance and data retention, supporting cost-effective manufacturing and efficient memory device production compatible with conventional processes.
Implementation Method 1
The charge trapping architecture offers improved scalability to new semiconductor processes compared to the floating gate architecture. One implementation of the charge trapping architecture is a silicon-oxide-nitride-oxide semiconductor (SONOS) where the charge is trapped in the nitride layer.
Implementation Method 2
The gate wraps around the fin like channel, thus it has increased gate control to reduce the short channel effect. The Fin FET concept can be applied to both floating gate and nitride based technology.
Implementation Method 3
Electrons can be injected and stored in the floating gate as well as erased using an electrical field or ultraviolet light. The stored information may be interpreted as a value '0' or '1' from the threshold voltage value depending upon charge stored in the floating gate.
Implementation Method 4
Electrons can be injected and stored in the floating gate as well as erased using an electrical field or ultraviolet light.
Data Source
AI summary
A method for manufacturing a memory system is provided including forming a charge-storage layer on a first insulator layer including insulating the charge-storage layer from a vertical fin, forming a second insulator layer from the charge-storage layer, and forming a gate over the second insulator includes forming a fin field effect transistor.