Fin-FET Fabrication Body-Bias Control via Segmented Substrate
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Solution Overview
Problem
Fin-FET semiconductor devices face challenges with ineffective body-bias control, high contact resistance, and susceptibility to mechanical damage due to the use of silicon-on-insulator substrates, which degrades performance and increases complexity and cost in fabrication.
Innovation Solution
The method involves forming a first insulation film in a trench of a semiconductor substrate, creating spacers to expose specific surface regions, and using these spacers as etch protection to form fins, which are then insulated and connected with a gate electrode, reducing contact resistance and enhancing body-bias control by supporting the fins and reducing mechanical damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If silicon-on-insulator substrates are used to form fin-FETs, then the fins are insulated from the bulk substrate bodies, but the threshold voltage cannot be effectively controlled using body-bias
Solution Approach 1:
The substrate is segmented into two distinct regions: a first substrate region that remains as bulk substrate for effective body-bias control, and a second substrate region that is removed to form the fin structure. This segmentation allows the fin-FET to maintain electrical connection with the bulk substrate for threshold voltage control while preserving the insulating benefits of the SOI structure in the fin region.
2Reliability
If conventional bulk substrate is used to allow for more effective body-bias control, then threshold voltage control is improved, but the drain depletion region extent increases causing increased junction leakage current and off current
Solution Approach 1:
Different substrate regions are assigned different electrical properties: the first substrate region maintains bulk characteristics for effective body-bias control, while the second substrate region is removed to create the fin structure with controlled depletion regions. This local differentiation allows effective threshold voltage control without excessive junction leakage.
3Ease of manufacture
If bit line contacts are formed across and contacting only the narrow top surfaces of the fins, then the fin structure is simple, but the contact resistance is very high
Solution Approach 1:
The contact structure transitions from two-dimensional top-surface contact to three-dimensional side-surface contact. Bit line contacts are formed to contact the side surfaces of the fins rather than only the narrow top surfaces, significantly increasing the contact area and reducing contact resistance while maintaining structural simplicity.
4Productivity
If the fins are made thinner to increase integration density, then device integration is improved, but the likelihood of mechanical damage and collapse increases
Solution Approach 1:
The fins are formed with controlled dimensions and structural integrity before subsequent processing steps. The fin structure is preliminarily established with appropriate width and height ratios, and supporting structures are prepared in advance to prevent mechanical damage and collapse during thinning and subsequent fabrication processes.
Data Source
AI summary
Provided are methods for fabricating semiconductor devices incorporating a fin-FET structure that provides body-bias control, exhibits some characteristic advantages associated with SOI structures, provides increased operating current and/or reduced contact resistance. The methods for fabricating semiconductor devices include forming insulating spacers on the sidewalls of a protruding portion of a first insulation film; forming a second trench by removing exposed regions of the semiconductor substrate using the insulating spacers as an etch mask, and thus forming fins in contact with and supported by the first insulation film. After forming the fins, a third insulation film is formed to fill the second trench and support the fins. A portion of the first insulation film is then removed to open a space between the fins in which additional structures including gate dielectrics, gate electrodes and additional contact, insulating and storage node structures may be formed.