Fin FET Strain Engineering via Segmented Layer Stack
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Solution Overview
Problem
The semiconductor industry faces challenges in implementing fin field effect transistors (Fin FETs) with strained materials in complementary metal-oxide-semiconductor (CMOS) fabrication, particularly in achieving effective stress application and precise control over fin structures for enhanced carrier mobility and device performance.
Innovation Solution
The use of fin structures with specific layer configurations, including a base layer, intermediate strain layers, and channel layers made of materials like SiGe, along with protective layers and strain-inducing SiGe oxide layers, to apply compressive and tensile stresses, and precise etching and deposition processes to form isolated and accurately dimensioned fin structures for improved mobility and control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If strained materials like SiGe are used in source/drain portions to enhance carrier mobility, then device performance is improved, but fabrication complexity and control difficulty increase
Solution Approach 1:
The fin structure is divided into multiple semiconductor layers with different materials and strain characteristics. The base layer, intermediate layer, and channel layer are segmented to provide different functions, with the intermediate layer specifically designed to induce strain in the channel region while the base layer provides structural support. This segmentation allows complex strain engineering to be achieved through modular layer construction rather than monolithic complex processing.
Solution Approach 2:
Strain is applied locally to specific regions of the fin structure through the intermediate semiconductor layer. The intermediate layer is positioned specifically between the base layer and channel layer to induce tensile or compressive strain in the channel region, while other regions maintain their original properties. This local application of strain allows mobility enhancement in the channel without requiring strained materials throughout the entire device structure.
2Manufacturing precision
If multiple protective layers are formed over fin structures, then manufacturing precision is improved, but process complexity increases
Solution Approach 1:
Protective layers are formed over the fin structures at predetermined stages during the fabrication process, before subsequent processing steps that require precise fin structure definition. The first protective layer is formed after the intermediate layer is created, and a second protective layer is formed later to protect during source/drain region processing. This preliminary protection prevents damage and maintains precision without requiring re-work or complex adjustment steps.
Solution Approach 2:
The protective layers serve as intermediary elements between the fin structure and the processing environment. These layers protect the precise fin structures from damage during subsequent fabrication steps such as source/drain formation and metallization. The protective layers are temporarily introduced and then removed or retained based on process requirements, acting as mediators that enable precise fin structure fabrication without exposing them to damaging processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances carrier mobility and control in Fin FETs, leading to improved device performance and manufacturing precision, addressing the challenges of stress application and structural precision in CMOS fabrication.
Implementation Method 1
strained materials in source/drain (S/D) portions of the Fin FET utilizing selectively grown silicon germanium (SiGe) may be used to enhance carrier mobility. For example, compressive stress applied to a channel of a PMOS device advantageously enhances hole mobility in the channel.
Data Source
AI summary
A semiconductor device includes a fin structure for a fin field effect transistor (FET). The fin structure includes a base layer protruding from a substrate, an intermediate layer disposed over the base layer and an upper layer disposed over the intermediate layer. The fin structure further includes a first protective layer and a second protective layer made of a different material than the first protective layer. The intermediate layer includes a first semiconductor layer disposed over the base layer, the first protective layer covers at least side walls of the first semiconductor layer and the second protective layer covers at least side walls of the first protective layer.