Fin FET Stress Material Layer for Carrier Mobility
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Solution Overview
Problem
Conventional methods for enhancing carrier mobility in fin FETs affect the electrical properties of the high-k gate dielectric layer, leading to increased gate leakage current and decreased gate breakdown voltage.
Innovation Solution
A semiconductor structure with a fin structure, a main gate structure, and a back gate structure, where a stress material layer is placed between the fin structure and the back gate structure to provide uniform stress to the channel region, thereby enhancing carrier mobility without affecting the electrical properties of the gate dielectric layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a stress metal layer is formed on the high-k gate dielectric layer to enhance carrier mobility, then carrier mobility in the channel region is improved, but electrical properties of the high-k gate dielectric layer are affected leading to increased gate leakage current and decreased gate breakdown voltage
Solution Approach 1:
The patent divides the stress application function from the gate dielectric layer by introducing a separate stress material layer. The gate dielectric layer is segmented into regions: a first region over the channel and a second region over the stress material layer. This segmentation allows the stress material layer to provide mechanical stress for carrier mobility enhancement while the gate dielectric layer maintains its electrical integrity without direct exposure to stress-induced damage.
Solution Approach 2:
The patent introduces an intermediary structure (the second region of the gate dielectric layer over the stress material layer) that acts as a buffer between the stress material layer and the channel region. This intermediary protects the electrical properties of the gate dielectric layer while still allowing the stress effect to be transmitted to enhance carrier mobility in the channel.
2Length of moving object
If the critical dimension of device is shrunk to improve device performance, then device scaling is achieved, but conventional MOS FET structure cannot meet performance requirements
Solution Approach 1:
The patent transitions from a planar MOS FET structure to a three-dimensional Fin FET structure with multiple gates. By adding vertical dimension (fin height) and multiple gating surfaces (top gate and sidewall gates), the device achieves better performance control at scaled dimensions. The multiple gates provide enhanced electrostatic control and driving current without requiring further reduction of critical dimensions.
Solution Approach 2:
The patent employs composite material structures including high-k gate dielectric layer combined with metal gate electrodes, and stress material layer integrated with the Fin FET structure. These composite materials enable the device to maintain performance requirements at scaled dimensions by providing enhanced electrical properties and mechanical stress control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves carrier mobility in the channel region while maintaining the electrical integrity of the gate dielectric layer, reducing gate leakage current and increasing gate breakdown voltage.
Implementation Method 1
a stress material layer is placed between the fin structure and the back gate structure to provide uniform stress to the channel region, thereby enhancing carrier mobility
Data Source
AI summary
Semiconductor devices and fabrication methods are provided. In an exemplary method, a semiconductor layer including a first opening can be provided. The first opening can be filled with a stress material. The stress material can then be etched to form a second opening having a width less than a width of the first opening to leave a stress material layer in the semiconductor layer and on each sidewall of the second opening. The semiconductor layer can be etched to form a fin structure on a sidewall surface of the stress material layer. A main gate structure can be formed on the sidewall surface of the fin structure. A back gate structure can be formed on the sidewall surface of the stress material layer.