Fin FET Stressor Layers for Carrier Mobility
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Solution Overview
Problem
In the semiconductor industry, the fabrication of fin field effect transistors (Fin FETs) faces challenges in achieving optimal carrier mobility and reducing short channel effects due to the complexity of forming strained source/drain regions with high aspect ratios and precise control over the gate-source/drain proximity.
Innovation Solution
The process involves forming a fin structure over a substrate, creating a recessed source/drain region with strain materials like SiGe, and using a multi-layer stressor structure to apply compressive stress to the channel layer, while adjusting etching conditions to control the proximity between the gate and source/drain epitaxial layers, thereby enhancing carrier mobility and reducing contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If strained materials are used in source/drain portions to enhance carrier mobility, then carrier mobility is improved, but the fabrication complexity increases due to the need for precise control over gate-source/drain proximity and high aspect ratio fin structures
Solution Approach 1:
The source/drain structure is segmented into multiple functional regions: the recessed region containing strain material for mobility enhancement, the epitaxial layer for controlled growth, and the contact region for electrical connection. This segmentation allows each region to be optimized independently, reducing fabrication complexity while maintaining carrier mobility benefits
Solution Approach 2:
The recessed source/drain region is formed preliminarily before epitaxial layer deposition. This preliminary action creates a pre-configured structure that guides subsequent material deposition and ensures precise control over gate-source/drain proximity, simplifying the overall fabrication process
2Area of moving object
If the fin structure has high aspect ratio to increase surface area, then device performance is improved, but manufacturing precision requirements increase due to challenges in forming and controlling such structures
Solution Approach 1:
An intermediary epitaxial layer is introduced between the substrate and the final device structure. This intermediary layer serves as a buffer that facilitates the formation of high aspect ratio fin structures by providing a controlled growth interface, thereby reducing manufacturing precision requirements while maintaining the desired surface area
Solution Approach 2:
The aspect ratio of the fin structure is optimized by adjusting key parameters including the depth and width of the recessed region, the thickness of the epitaxial layer, and the strain material composition. These parameter changes enable achievement of high surface area with relaxed manufacturing precision constraints
3Reliability
If the gate is formed over and along the sides of the fin structure to wrap around it, then device control is improved, but the proximity control between gate and source/drain becomes more difficult to achieve
Solution Approach 1:
The gate structure is segmented into distinct portions: the main gate body formed over the fin structure and side extensions that wrap around the fin sides. This segmentation allows independent optimization of each gate portion, improving device control while simplifying proximity control between gate and source/drain regions
Solution Approach 2:
The recessed source/drain region is formed preliminarily with precise dimensions before gate deposition. This preliminary action establishes a pre-defined proximity relationship between the gate and source/drain, making the subsequent gate formation process more straightforward and reducing manufacturing precision requirements
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves carrier mobility and suppresses short channel effects, leading to more reliable and efficient Fin FET devices with enhanced performance.
Implementation Method 1
each including a stressor layer disposed in a recess in the fin structure not covered by the gate structure. The stressor layer includes a first stressor layer and a second stressor layer overlying the first stressor layer
Data Source
AI summary
A p-type semiconductor Fin FET device includes a fin structure disposed over a substrate. The fin structure includes a channel layer. The Fin FET device also includes a gate structure including a gate electrode layer and a gate dielectric layer, covering a portion of the fin structure. Side-wall insulating layers are disposed over both main sides of the gate electrode layer. The Fin FET device includes a source and a drain, each including a stressor layer disposed in a recess formed by removing the fin structure not covered by the gate structure. The stressor layer includes a first stressor layer and a second stressor layer formed in this order. In the source, an interface between the first stressor layer and the channel layer is located under one of the side-wall insulating layers closer to the source or the gate electrode.