Fin-FET Vertical Channel Fabrication for Short Channel Effects
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Solution Overview
Problem
Semiconductor devices, particularly fin-FETs, face challenges with short channel effects and narrow width effects due to reduced gate and channel widths, leading to performance issues such as drain induced barrier lowering and reduced drain current.
Innovation Solution
A method of fabricating semiconductor devices involving the formation of first and second gate patterns on a semiconductor substrate, with a device isolation layer and vertically protruding fins, where the gate electrode covers the fins and device isolation layer, and a gate insulating layer is conformally applied to the fins, improving channel width and reducing short channel effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the width of the gate electrode and active region is reduced for high integration, then the device density increases, but short channel effects (DIBL and punch-through) and narrow width effects (reduced drain current) occur
Solution Approach 1:
The patent transitions from a planar channel structure to a vertical fin channel structure. The channel extends vertically along the fin height rather than horizontally under the gate, effectively adding a vertical dimension to the channel transport path. This allows the channel length to be decoupled from the gate width, enabling high integration density while maintaining adequate channel length to suppress short channel effects.
Solution Approach 2:
The gate electrode is designed to control three surfaces of the channel region (top surface and two sidewalls) through the vertical fin structure, providing enhanced local control over the channel. This three-sided gate control improves the effectiveness of the gate in modulating the channel conductivity while maintaining compact device footprint.
2Productivity
If the width of the active region is reduced to increase integration, then the channel width is reduced, but the drain current decreases due to narrow width effect
Solution Approach 1:
The channel current transport is redirected from a horizontal path (limited by gate width) to a vertical path along the fin height. This dimensional change allows the effective channel cross-sectional area for current flow to be determined by fin width × fin height rather than gate width × channel thickness, enabling higher current density in a smaller footprint.
Solution Approach 2:
The fin structure utilizes a composite approach with a semiconductor fin region (providing channel formation) surrounded by device isolation regions. This composite structure enables the vertical channel to be formed while maintaining electrical isolation between adjacent devices, allowing high integration without compromising current flow.
3Reliability
If a vertical fin channel structure is used to improve short channel effects and narrow width effects, then channel width is increased in limited area, but fabrication process complexity increases
Solution Approach 1:
The fabrication process is segmented into distinct stages: forming fins in the semiconductor substrate, forming device isolation regions in trenches between fins, and forming the gate electrode structure. This segmentation allows each component to be optimized independently while maintaining overall process simplicity and compatibility with existing CMOS fabrication techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the fabrication process and enhances the performance of semiconductor devices by effectively addressing short channel and narrow width effects, improving the channel width and reducing performance issues like drain induced barrier lowering and reduced drain current.
Implementation Method 1
performing a thermal oxidation process on the semiconductor substrate to form a gate insulating layer conformally covering surfaces of the fins
Implementation Method 2
the etch mask pattern may include a material having an etch selectivity with respect to the insulating layer and the second gate pattern
Data Source
AI summary
A method of fabricating a semiconductor device includes forming first gate patterns on a semiconductor substrate using an etch mask pattern, forming a trench in the semiconductor substrate between the first gate patterns, forming an insulating layer in the trench, such that the insulating layer fills the trench and is disposed on the etch mask pattern, planarizing the insulating layer until a top surface of the etch mask pattern is exposed, etching a portion of the planarized insulating layer to form a device isolation layer in the trench, forming a second gate layer covering the etch mask pattern and disposed on the device isolation pattern, and planarizing the second gate layer until the top surface of the etch mask pattern is exposed, such that a second gate pattern is formed.