Semiconductor Fin Gate Isolation With Air Gaps for Lower Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor IC chip technologies face challenges in improving electrical characteristics, particularly in reducing device capacitance to minimize resistive-capacitive delay, despite advancements in scaling and functional density.
Innovation Solution
The process involves forming a refill dielectric layer with an oxygen-free high-k dielectric material in CMG trenches, creating air gaps within the refill dielectric layer to lower the overall dielectric constant and reduce capacitance, while preventing oxidation of gate stacks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional dielectric materials are used in CMG trenches, then the manufacturing process is simple, but the device capacitance is high causing increased resistive-capacitive delay
Solution Approach 1:
The patent applies composite materials by combining oxygen-free high-k dielectric material with air gaps to create a composite dielectric structure. This composite structure achieves lower effective capacitance than conventional homogeneous dielectric materials while managing the complexity through controlled fabrication processes.
Solution Approach 2:
The patent introduces air gaps (porous structures) within the refill dielectric layer to reduce the overall dielectric constant. This porous approach lowers device capacitance by replacing solid dielectric material with air-filled voids, directly addressing the capacitance reduction goal.
2Loss of energy
If oxygen-free high-k dielectric material is deposited in CMG trenches, then capacitance is reduced, but oxidation of gate stacks may occur
Solution Approach 1:
The patent uses oxygen-free high-k dielectric material to create an inert environment within the CMG trenches. This oxygen-free atmosphere prevents oxidation of the gate stacks while maintaining the capacitance reduction benefits, directly resolving the contradiction between capacitance lowering and oxidation prevention.
Solution Approach 2:
The oxygen-free high-k dielectric material acts as an intermediary barrier between the gate stacks and oxidizing environments. This intermediate layer protects the gate stacks from oxidation while still providing the desired capacitance reduction through its high-k properties and air gap structure.
3Loss of energy
If air gaps are created in refill dielectric layer, then overall dielectric constant is lowered, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs preliminary actions by using sacrificial layers and controlled deposition processes to pre-establish the air gap structure before final dielectric layer formation. This preliminary structuring simplifies the overall manufacturing precision requirements by guiding subsequent processing steps.
Solution Approach 2:
The patent applies the extraction principle by removing sacrificial materials to create air gaps within the refill dielectric layer. This extraction approach allows precise control over air gap formation and positioning, managing manufacturing precision requirements through a controlled removal process rather than direct gap formation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively lowers the overall capacitance of the semiconductor device by 1% to 2%, enhancing electrical characteristics and reducing device dimensions.
Implementation Method 1
forming a refill dielectric layer with an oxygen-free high-k dielectric material in CMG trenches, creating air gaps within the refill dielectric layer to lower the overall dielectric constant and reduce capacitance, while preventing oxidation of gate stacks
Implementation Method 2
creating air gaps within the refill dielectric layer to lower the overall dielectric constant and reduce capacitance
Data Source
AI summary
A semiconductor device includes a plurality of semiconductor fins, at least one gate stack, a refill isolation, and an air gap. Each of the semiconductor fins extends in an X direction. Two adjacent ones of the semiconductor fins are spaced apart from each other in a Y direction transverse to the X direction. The at least one gate stack has two stack sections spaced apart from each other in the Y direction. The stack sections are disposed over two adjacent ones of the semiconductor fins, respectively. The refill isolation and the air gap are disposed between the stack sections.