Fin Gate Dielectric Thickness Profile for Dummy Gate Etch Protection

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Solution Overview

Problem

Conventional semiconductor fabrication processes face challenges in completely removing dummy polysilicon gate electrodes without damaging fin structures, leading to fin top loss and reduced device performance or yield, especially as device sizes shrink.

Innovation Solution

A protective layer with a top-thick-side-narrow profile is formed over fin structures, using deposition and etching processes to ensure complete removal of the dummy gate electrode while maintaining fin-to-fin spacing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If robust etching processes are used to completely remove dummy polysilicon gate electrodes, then removal completeness is improved, but fin structure damage increases

Engineering Contradiction:
Improvedummy gate electrode removal completenessVSAvoidfin structure damage
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

A sacrificial dielectric layer is introduced as an intermediary protective element between the dummy polysilicon gate electrode and the fin structure. This sacrificial layer absorbs the etching action, allowing complete removal of the dummy gate electrode while preventing direct contact and damage to the fin structure. The sacrificial dielectric layer is selectively removed after serving its protective function.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The sacrificial dielectric layer is formed in advance before the etching process that removes the dummy gate electrode. This preliminary protective action ensures that when the robust etching process is applied, the fin structure is already shielded, enabling complete dummy gate removal without subsequent fin damage.

Inventive Principle:
Principle #10Preliminary action

2Object-affected harmful factors

If conventional protective methods are used to prevent fin height loss, then fin structure protection is improved, but spacing between adjacent fins decreases

Engineering Contradiction:
Improvefin height loss preventionVSAvoidfin-to-fin spacing
Core Design Contradiction:
Object-affected harmful factorsVSLength of moving object

Solution Approach 1:

The protective function is segmented and localized to only the regions where dummy gate electrodes are present. The sacrificial dielectric layer is formed selectively over specific fin structures that require protection during dummy gate removal, rather than applying a uniform protective layer across all fins. This segmentation maintains fin-to-fin spacing in unprotected regions while providing protection where needed.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach prevents fin top loss and enhances device performance and yield by allowing more robust etching without affecting fin structures, while maintaining sufficient spacing between adjacent fins.

Implementation Method 1

A first dielectric layer is formed over an upper surface and side surfaces of a fin structure

Methodology Applied
Scientific EffectPhysical Vapour Deposition: Physical Vapour Deposition

Implementation Method 2

a first dielectric layer is formed over an upper surface and side surfaces of a fin structure that contains a semiconductor material

Methodology Applied
Scientific EffectChemical Vapour Deposition: Chemical Vapour Deposition

Implementation Method 3

The mask layer is etched away to expose portions of the fin structure

Methodology Applied
Scientific EffectEtching:

Implementation Method 4

an oxidation process is performed to convert the mask layer into a dielectric material

Methodology Applied
Scientific EffectOxidation: Oxidation

Data Source

PatentUS20260090085A1Gate Dielectric Having A Non-Uniform Thickness Profile
Publication Date: 2026.03.26 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20260090085A1 patent drawing
  • US20260090085A1 patent drawing
  • US20260090085A1 patent drawing

AI summary

A first dielectric layer is formed over upper and side surfaces of a semiconductor fin structure. A mask layer is formed over a first portion of the first dielectric layer disposed over the upper surface of the fin structure. The mask layer and the first dielectric layer have different material compositions. Second portions of the first dielectric layer disposed on side surfaces of the fin structure are etched. The mask layer protects the first portion of the first dielectric layer from being etched. A second dielectric layer is formed over the mask layer and the side surfaces of the fin structure. An oxidation process is performed to convert the mask layer into a dielectric material having substantially a same material composition as the first or second dielectric layer. The dielectric material and remaining portions of the first or second dielectric layer collectively serve as a gate dielectric of a transistor.