Non-Uniform Fin Gate Dielectric for Dummy Gate Etching
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Solution Overview
Problem
Conventional semiconductor fabrication methods face challenges in completely removing dummy polysilicon gate electrodes without damaging fin structures, leading to fin top loss and reduced device performance or yield, especially as device sizes shrink.
Innovation Solution
A protective layer with a top-thick-side-narrow profile is formed over fin structures, using deposition and etching processes to ensure complete removal of the dummy gate electrode while maintaining fin integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional etching processes are used to remove dummy polysilicon gate electrodes, then complete removal of the dummy gate electrode is achieved, but fin structures suffer unintended damage and loss of fin height
Solution Approach 1:
A protective oxide layer is formed over the fin structures before the etching process. This preliminary protective action allows the subsequent etching to completely remove the dummy gate electrode while the oxide layer prevents the etching from damaging the fin structures, thus resolving the contradiction between complete removal and fin integrity
Solution Approach 2:
The protective oxide layer acts as an intermediary between the etching process and the fin structures. It enables the etching to proceed against the dummy gate electrode while blocking direct contact between the etching chemicals and the fin structures, thereby allowing complete removal without fin damage
2Reliability
If protective oxide layer is formed over fin structures, then fin top loss is prevented, but fin-to-fin spacing is reduced
Solution Approach 1:
The protective oxide layer is formed with non-uniform thickness - thicker at the top of the fin structures and thinner at the sides. This local variation in thickness provides adequate protection at the fin tops while minimizing the reduction of fin-to-fin spacing at the sides, thus resolving the contradiction between fin integrity and spacing maintenance
3Productivity
If device geometry is scaled down to increase functional density, then production efficiency increases and costs lower, but etching processes cause unintended damage to fin structures
Solution Approach 1:
The protective oxide layer is formed before scaling-down etching processes. This preliminary protective measure enables the use of more aggressive etching conditions needed for scaled-down devices while preventing the etching from damaging the fin structures, thus allowing improved productivity without increased fin damage
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents fin top loss and maintains sufficient fin-to-fin spacing, enhancing device performance and yield by allowing harder etching without damaging the fin structures.
Implementation Method 1
A protective layer with a top-thick-side-narrow profile is formed over fin structures, using deposition and etching processes
Implementation Method 2
using deposition and etching processes to ensure complete removal of the dummy gate electrode while maintaining fin integrity
Data Source
AI summary
A first dielectric layer is formed over upper and side surfaces of a semiconductor fin structure. A mask layer is formed over a first portion of the first dielectric layer disposed over the upper surface of the fin structure. The mask layer and the first dielectric layer have different material compositions. Second portions of the first dielectric layer disposed on side surfaces of the fin structure are etched. The mask layer protects the first portion of the first dielectric layer from being etched. A second dielectric layer is formed over the mask layer and the side surfaces of the fin structure. An oxidation process is performed to convert the mask layer into a dielectric material having substantially a same material composition as the first or second dielectric layer. The dielectric material and remaining portions of the first or second dielectric layer collectively serve as a gate dielectric of a transistor.