Fin-Type Gate Electrode Thickness Control for Threshold Voltage Tuning
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Solution Overview
Problem
Current integrated circuit devices face challenges in achieving distinct threshold voltages for fin field-effect transistors due to limitations in gate electrode thickness and material differences, which affect the operational efficiency and scalability of semiconductor devices.
Innovation Solution
The integration of fin field-effect transistors with gate structures having different thicknesses and materials for the gate electrodes, where the first gate electrode has a specific thickness and the second gate electrode has a distinct thickness, differing by up to 1 nm, allowing for the formation of NMOS transistors with varying threshold voltages, and the use of spacers and gap-filling metal layers to define recess spaces and enhance the gate structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If gate electrode thickness is varied to achieve different threshold voltages, then transistor threshold voltage control is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies local quality by forming gate electrodes with different thicknesses in different regions. Specifically, a first gate electrode is formed with a first thickness in a first region, and a second gate electrode is formed with a second thickness in a second region, allowing different threshold voltages to be achieved in different transistor regions through localized thickness variation
Solution Approach 2:
The gate electrode structure is segmented into multiple regions with different thickness characteristics. The first gate electrode and second gate electrode are formed as separate segments with controlled thickness differences, enabling independent threshold voltage tuning for different transistor types (e.g., NMOS and PMOS) without affecting the entire gate structure uniformly
2Adaptability or versatility
If multiple gate structures with different thicknesses are formed, then device functionality is improved, but device complexity increases
Solution Approach 1:
The gate electrode structure is designed to serve multiple functions simultaneously. The first and second gate electrodes with different thicknesses enable different transistor regions to operate with different threshold voltages, allowing a single gate structure to control both NMOS and PMOS transistors with optimized performance for each transistor type
Data Source
AI summary
Integrated circuit devices include a substrate including first and second fin-type active regions and first and second gate structures. The first gate structure includes first gate insulating layer on the first fin-type active region to cover upper surface and both side surfaces of the first fin-type active region, first gate electrode on the first gate insulating layer and has first thickness in first direction perpendicular to upper surface of the substrate, and second gate electrode on the first gate electrode. The second gate structure includes second gate insulating layer on the second fin-type active region to cover upper surface and both side surfaces of the second fin-type active region, third gate insulating layer on the second gate insulating layer, third gate electrode on the third gate insulating layer and has second thickness different from the first thickness in the first direction, and fourth gate electrode on the third gate electrode.