Fin-Type Gate Electrode Width Profile for Semiconductor Scaling
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Solution Overview
Problem
Current multi-gate transistors face challenges in scaling and maintaining performance due to short channel effects and issues with gate electrode filling, leading to reliability concerns and reduced proximity between the gate and source/drain regions.
Innovation Solution
A semiconductor device design featuring a fin-type pattern with a gate electrode having a triangular flask shape, where the first portion's width increases, the second portion's width decreases, and the third portion's width remains constant or increases, with a field insulating film and gate spacer configuration that enhances the gate's proximity to the source and drain regions, preventing incomplete filling of conductive films.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a conventional multi-gate transistor is scaled down, then device density increases, but short channel effects worsen and gate electrode filling becomes incomplete
Solution Approach 1:
The gate electrode is divided into three distinct portions (first, second, and third portions) with different width characteristics. This segmentation allows each portion to address specific filling challenges at different locations along the gate structure, ensuring complete conductive film deposition even in scaled-down devices where conventional uniform gates fail to fill properly.
Solution Approach 2:
Different portions of the gate electrode have different width characteristics tailored to local requirements. The first portion has increasing width to ensure filling at the base, the second portion has decreasing width to control overhang, and the third portion has constant or increasing width to maintain proximity. This local quality variation solves the global filling problem by addressing specific local challenges.
2Reliability
If the gate length is increased to suppress short channel effects, then SCE suppression improves, but device scaling capability deteriorates
Solution Approach 1:
Instead of increasing gate length in one dimension to suppress SCE, the invention uses a three-dimensional gate structure with varying widths along the gate direction. This dimensional approach allows effective SCE suppression through improved gate control over the channel while maintaining compact device footprint and scaling capability.
Solution Approach 2:
The gate electrode width parameter is changed along its length, transitioning from uniform width in conventional designs to a varying width profile with three distinct portions. This parameter variation enables effective electrostatic control for SCE suppression while maintaining the scaled-down device dimensions required for high density.
3Ease of manufacture
If the gate electrode width is uniform, then manufacturing is simpler, but conductive film filling becomes incomplete in scaled devices
Solution Approach 1:
The gate electrode is pre-formed with a specific non-uniform width profile before conductive film deposition. This preliminary shaping of the gate structure ensures that the subsequent conductive film filling process can complete successfully, preventing the incomplete filling that occurs with uniform width gates in scaled devices.
Solution Approach 2:
The gate electrode employs an asymmetric width profile with three distinct portions rather than a symmetric uniform width. This asymmetry is deliberately introduced to solve the filling problem, where the varying width creates favorable geometry for complete conductive film deposition while maintaining manufacturing feasibility through standard lithography and etching processes.
4Reliability
If the gate proximity to source/drain regions is increased, then current control capability improves, but device area increases
Solution Approach 1:
The gate electrode width parameter is varied along its length to optimize the proximity to source and drain regions. By having the third portion with constant or increasing width, the gate maintains close proximity to the regions where it is most needed for current control, while the overall gate structure remains compact, avoiding excessive device area expansion.
Data Source
AI summary
A semiconductor device is provided. The semiconductor device includes a fin type pattern, a field insulating film on a part of a sidewall of the fin-type pattern, and a gate electrode intersecting with the fin-type pattern, on the fin-type pattern and the field insulating film. The gate electrode on the field insulating film includes a first portion, a second portion, and a third portion on the field insulating film. A first width of the first portion increases as a first distance from the field insulating film, increases width of the second portion decreases as a second distance from the field insulating film increases, and a third width of the third portion increases or is substantially constant as a third distance from the field insulating film increases.