Fin Structure Height Variation for Precise FinFET Patterning
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Solution Overview
Problem
The semiconductor industry faces challenges in forming reliable semiconductor devices at smaller sizes due to increased complexity and difficulty in fabrication processes as feature sizes decrease, requiring innovative methods to pattern fins for FinFET structures effectively.
Innovation Solution
The method involves forming fins using photolithography and self-aligned processes, such as double-patterning or multi-patterning, with spacer layers and etching techniques to create fin structures with varying heights and spacer elements, allowing for epitaxial growth of merged and isolated semiconductor elements, which improves electrical properties and reduces fabrication costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photolithography and self-aligned processes are used to form fins, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent divides the fin formation process into multiple discrete steps including forming sacrificial fins, depositing spacer layers, selectively removing portions, and repeating the process. This segmentation allows each step to be optimized independently while achieving high overall precision in the final fin structure.
Solution Approach 2:
The patent employs preliminary actions by first forming sacrificial fin structures and spacer layers before actually creating the final fin geometry. These preliminary structures serve as templates that guide subsequent etching and material deposition, ensuring precise fin formation while simplifying the control of complex processes.
2Productivity
If feature sizes are decreased to increase functional density, then productivity is improved, but manufacturing precision becomes more difficult to achieve
Solution Approach 1:
The patent utilizes self-aligned processes where previously formed structures automatically serve as alignment references for subsequent steps. The spacer layers form conformally on the sacrificial fins, and the etch processes use the spacers as masks, eliminating the need for separate alignment operations and maintaining precision at reduced feature sizes.
Solution Approach 2:
The patent changes physical and chemical parameters throughout the process, including using different materials for sacrificial fins versus final fins, varying spacer layer thicknesses, and adjusting etch selectivities. These parameter changes enable precise control over fin dimensions and spacing even as overall feature sizes decrease to increase functional density.
3Reliability
If multiple patterning processes are used to create varying fin heights, then device performance is improved, but fabrication complexity increases
Solution Approach 1:
The patent merges multiple functions into unified process steps. For example, the same spacer deposition and etch processes that create the fin structures also simultaneously create the varying fin heights and integrate the source/drain regions. This merging reduces the total number of discrete fabrication steps while achieving complex three-dimensional fin geometries.
Solution Approach 2:
The patent uses spacer layers as intermediary structures that mediate between the sacrificial fins and the final fin geometry. These spacers serve multiple roles: defining fin positions, controlling fin heights through their thickness, and serving as etch masks. This intermediary approach simplifies the overall process by using a single reusable structure type to control multiple geometric parameters.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of semiconductor devices with improved electrical properties by creating merged and isolated semiconductor elements with controlled epitaxial growth, enhancing resistance and device performance while reducing fabrication complexity and costs.
Implementation Method 1
forming fins using photolithography and self-aligned processes
Implementation Method 2
allowing for epitaxial growth of merged and isolated semiconductor elements
Data Source
AI summary
A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a first fin structure and a second fin structure over the substrate. A top surface of the first fin structure and a top surface of the second fin structure are at different height levels. The semiconductor device structure also includes a first semiconductor element on the first fin structure and a second semiconductor element on the second fin structure. The first semiconductor element is wider than the second semiconductor element, and the first semiconductor element is closer to the substrate than the second semiconductor element.