Fin Height Maintenance in Semiconductor Memory Devices
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Solution Overview
Problem
In fin-type nonvolatile memory cells, the ON-current matching the initial height of the fin cannot be secured, leading to deteriorated reading and writing characteristics due to the reduction in fin height caused by the film thickness of the gate insulating films and the ONO film, which affects the overlap range of the memory gate electrode and the fin.
Innovation Solution
The semiconductor device includes a control gate electrode and a memory gate electrode with a second gate insulating film of an ONO film structure, where the element separation film is formed with a thinner main surface to increase the fin height contributing to the ON-current, ensuring better overlap and thus improved reading and writing characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a standard thickness element separation film is formed, then the gate insulating films and ONO film can be properly formed, but the fin height contributing to ON-current is reduced
Solution Approach 1:
The element separation film is configured with different thicknesses in different regions: a first thickness in the region overlapping the control gate electrode and a second thickness (greater than the first) in the region overlapping the memory gate electrode. This local differentiation allows the fin height contributing to ON-current to be maintained in the memory transistor region while still providing proper gate insulating film formation.
Solution Approach 2:
The solution transitions from a uniform two-dimensional film structure to a three-dimensional structure with variable thickness. By creating a stepped or graded thickness profile in the element separation film, the patent achieves different fin heights in different regions without requiring separate fabrication processes for each region.
2Reliability
If thicker gate insulating films are used, then reliability is improved, but the overlap range between memory gate electrode and fin is reduced
Solution Approach 1:
The gate insulating films are formed with different thicknesses in different regions: a first thickness in the control transistor region and a second thickness (greater than the first) in the memory transistor region. This allows the memory transistor to have enhanced reliability through thicker gate insulating films while the control transistor maintains its original characteristics.
Solution Approach 2:
The element separation film is formed with predetermined variable thickness before forming the gate insulating films. This preliminary structuring enables subsequent gate insulating films to be formed with appropriate thicknesses in different regions, ensuring both reliability and sufficient overlap range are achieved.
3Volume of moving object
If the fin height is reduced by film thickness, then the device can be miniaturized, but the ON-current matching the initial fin height cannot be secured
Solution Approach 1:
The element separation film and gate insulating films are configured with spatially varying thicknesses to maintain the fin height contributing to ON-current in the memory transistor region. This local enhancement ensures that despite overall device miniaturization, the critical ON-current characteristic is preserved.
Solution Approach 2:
The patent converts the potentially harmful effect of reduced fin height (caused by multiple film layers) into a benefit by strategically positioning thicker element separation film regions. This transforms what would be a uniform degradation into a localized enhancement that improves ON-current while maintaining miniaturization elsewhere.
Data Source
AI summary
A semiconductor device includes a semiconductor substrate including a main surface, an element separation film formed over the main surface, and a fin protruding from the element separation film and extending in the first direction in plan view. The semiconductor device further includes a control gate electrode extending in the second direction that is orthogonal to the first direction along the surface of the fin through a gate insulating film and overlaps with a first main surface of the element separation film, and a memory gate electrode extending in the second direction along the surface of the fin through an insulating film and overlaps with a second main surface of the element separation film, in which the second main surface is lower than the first main surface relative to the main surface.