Fin Structure Height Variation for Off-Leak Current Suppression
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Solution Overview
Problem
Fin-type MOSFETs face challenges in suppressing off-leak current, specifically punch-through, which degrades cut-off characteristics due to the fine structure and current driving ability limitations.
Innovation Solution
A semiconductor device with a Fin structure featuring a channel region of greater height than the extension regions, covered by an insulation film and a gate electrode, along with specific doping and spacer formation techniques to create source, drain, and extension regions, effectively reducing off-leak current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a Fin structure is used to maintain current driving ability, then current driving ability is improved, but off-leak current increases due to punch-through
Solution Approach 1:
The patent applies local quality by creating a height difference between the channel region and extension regions. The channel region maintains a greater Fin height to preserve current driving ability, while the extension regions have reduced Fin height to suppress punch-through and off-leak current. This localized structural variation allows each region to optimize its function independently.
Solution Approach 2:
The Fin structure is segmented into distinct regions with different heights: the channel region and extension regions are separated by etching the extension regions to a lower height. This segmentation allows the channel to maintain full height for current conduction while the extension regions are shortened to prevent carrier punch-through, thereby resolving the contradiction between current driving ability and off-leak current suppression.
2Reliability
If the channel region height is increased to suppress punch-through, then cut-off characteristics improve, but manufacturing complexity increases
Solution Approach 1:
The patent employs preliminary action by forming the height difference between channel and extension regions during the Fin formation process itself. The mask layer is strategically positioned to protect the channel region during etching, while the extension regions are etched to a lower height. This preliminary structuring simplifies subsequent processing steps and reduces overall manufacturing complexity despite the enhanced structural features.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively suppresses punch-through and enhances current driving ability by increasing the channel region's height relative to the extension regions, reducing off-leak current and improving cut-off characteristics.
Implementation Method 1
an insulation film that covers both side surfaces and an upper surface of the channel region
Implementation Method 2
a gate electrode that covers the channel region via the insulation film
Implementation Method 3
a first extension region which is formed between the source region and the drain region within the Fin in contact with the source region, the first extension region having a lower impurity concentration than the source region
Data Source
AI summary
A semiconductor device includes a Fin, a source region and a drain region, a first extension region, a second extension region and a channel region. The Fin is formed on a major surface of a semiconductor substrate. The source region and drain region are formed at both end portions of the Fin. The first extension region is formed between the source region and the drain region within the Fin in contact with the source region. The second extension region is formed between the source region and the drain region within the Fin in contact with the drain region. The channel region is located between the first extension region and the second extension region within the Fin, a height of the Fin of the channel region being greater than a height of the Fin of each of the first extension region and the second extension region.


