Fin HEMT Gate Structure for Leakage and Threshold Control
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Solution Overview
Problem
Existing compound semiconductor devices face challenges in optimizing performance due to high leakage current and difficulty in controlling frequency characteristics, drain current, and threshold voltage, particularly in high electron mobility transistor (HEMT) devices.
Innovation Solution
A compound semiconductor device design featuring a fin structure with a first semiconductor layer, an upper gate electrode, a second semiconductor layer with a different bandgap, and a dielectric layer, along with a lower gate structure connected through the substrate, which creates a 2-dimensional electron gas region adjacent to the fin sidewalls, reducing leakage current and allowing for controlled performance modulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional HEMT device structure is used, then high electron mobility is achieved through 2 DEG layer, but leakage current increases and control over frequency characteristics and drain current becomes difficult
Solution Approach 1:
The device is divided into multiple semiconductor layers with different bandgaps (first semiconductor layer with first bandgap, second semiconductor layer with second bandgap greater than the first). This segmentation creates distinct functional regions that control electron flow and reduce leakage current while maintaining high electron mobility in the channel region.
Solution Approach 2:
Different regions of the device are assigned different material properties and bandgap characteristics. The first semiconductor layer provides high electron mobility in the channel, while the second semiconductor layer with wider bandgap provides barrier control and leakage reduction. The hetero-interface between these layers creates localized 2 DEG regions with specific electrical properties.
2Adaptability or versatility
If semiconductor layers with different energy bandgaps are attached to optimize performance, then high electron mobility is achieved, but control over frequency characteristics and threshold voltage becomes difficult
Solution Approach 1:
The device structure enables dynamic control of electrical characteristics through the hetero-interface between semiconductor layers with different bandgaps. The 2 DEG layer generated at this interface allows for adjustable electron concentration and mobility, enabling control over frequency characteristics and threshold voltage while maintaining adaptability for various performance requirements.
Solution Approach 2:
By changing the bandgap parameters of the semiconductor layers (first bandgap vs. second bandgap), the device can be optimized for different performance characteristics. The energy band discontinuity at the hetero-interface creates controllable potential barriers that adjust electron flow, enabling variability in performance while maintaining ease of control over frequency and voltage characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively decreases leakage current and enhances control over frequency characteristics, drain current, and threshold voltage, enabling variable performance optimization in HEMT devices.
Implementation Method 1
a 2-dimensional electron gas (2 DEG) layer generated by polarization and band-discontinuity close to the hetero-interface
Implementation Method 2
a 2-dimensional electron gas (2 DEG) layer generated by polarization and band-discontinuity close to the hetero-interface
Data Source
AI summary
Provided is a compound semiconductor device. The compound semiconductor device according to embodiments of the inventive concept includes a first semiconductor layer having a fin extending in a first direction on a substrate, an upper gate electrode extending in a second direction perpendicular to the first direction on the first semiconductor layer, a second semiconductor layer disposed between a sidewall of the fin and the upper gate electrode, a dielectric layer disposed between a top surface of the fin and the upper gate electrode, and a lower gate structure connected to a bottom surface of the first semiconductor layer by passing through the substrate.