Fin-Type IC Layout With Selective Insulation for Defect Control

Solution Overview

Problem

As integrated circuit devices become more densely integrated and smaller in size, the probability of defects during manufacturing increases, compromising the accuracy and operating speed of these devices.

Innovation Solution

The integrated circuit device incorporates a design with first and second fin-type active regions, nanosheet stacks, gate lines, source/drain regions, spacer structures, and protective insulating films to enhance reliability and performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If integration density is increased and device size is decreased, then productivity and compactness are improved, but manufacturing precision and reliability deteriorate due to increased defect probability

Engineering Contradiction:

Improveintegration densityVSAvoiddefect probability

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The device is divided into first and second fin-type active regions with separate source/drain regions, allowing independent optimization and manufacturing control of each segment, thereby reducing the impact of defects on the entire device

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different regions of the device are given different structures and properties - the first fin-type active region has a first source/drain region while the second fin-type active region has a second source/drain region, enabling localized optimization for reliability at critical positions

Inventive Principle:

Principle #3Local quality

2Volume of moving object

If device size is decreased, then compactness is improved, but manufacturing precision deteriorates due to increased defect probability

Engineering Contradiction:

Improvedevice sizeVSAvoiddefect probability

Core Design Contradiction:

Volume of moving objectVSManufacturing precision

Solution Approach 1:

The patent transitions from planar device structures to three-dimensional fin-type active regions with vertical nanosheet stacks, allowing increased integration density without proportionally increasing the footprint area, thus maintaining manufacturing precision while improving compactness

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

Multiple nanosheet stacks are nested vertically within the fin-type active regions, enabling multiple functional elements to be packed into a compact volume while maintaining adequate spacing for manufacturing precision

Inventive Principle:

Principle #7Nested doll (Nesting)

3Productivity

If integration density is increased, then productivity is improved, but manufacturing precision deteriorates

Engineering Contradiction:

Improveintegration densityVSAvoiddefect probability

Core Design Contradiction:

ProductivityVSManufacturing precision

Solution Approach 1:

The device is divided into first and second fin-type active regions with separate source/drain regions, allowing independent optimization and manufacturing control of each segment, thereby reducing the impact of defects on the entire device

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent transitions from planar device structures to three-dimensional fin-type active regions with vertical nanosheet stacks, allowing increased integration density without proportionally increasing the footprint area, thus maintaining manufacturing precision while improving compactness

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS20250133791A1Integrated circuit device

Publication Date: 2025.04.24 SAMSUNG ELECTRONICS CO LTD

AI summary

An integrated circuit device includes a first fin-type active region and a second fin-type active region, each extending on a substrate in a first horizontal direction, a plurality of gate lines on the first fin-type active region and second fin-type active region, the plurality of gate lines extending in a second horizontal direction that crosses the first horizontal direction, a first source/drain region and a second source/drain region respectively in the first fin-type active region and second fin-type active region, wherein each of the first source/drain region and the second source/drain region is disposed between the plurality of gate lines, a spacer structure disposed on the plurality of gate lines, the first source/drain region and the second source/drain region, and a protective insulating film disposed on the second source/drain region and exposing the first source/drain region.