Fin-Insulating Structure for CPP Scaling Without Contact Bridging
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Solution Overview
Problem
Existing techniques for scaling contacted poly pitch (CPP) in semiconductor manufacturing, such as the continuous poly on diffusion edge (CPODE) process, face challenges like short circuits due to bridging of adjacent source/drain contacts during etching, which degrades device performance and reliability.
Innovation Solution
A method involving a CPODE process with a fin-insulating structure formed using a dry etching process, followed by filling with dielectric materials like silicon nitride, to isolate neighboring active regions and prevent bridging, while maintaining effective gate control and scaling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the continuous poly on diffusion edge (CPODE) process is used to scale contacted poly pitch (CPP), then the gate pitch is reduced and device density is increased, but adjacent source/drain contacts may bridge during etching causing short circuits and device failure
Solution Approach 1:
The patent divides the continuous poly structure into segmented regions by forming isolated insulating structures between adjacent active regions. This segmentation prevents the bridging of source/drain contacts during etching while maintaining the scaled gate pitch, thus resolving the contradiction between increased device density and device reliability
Solution Approach 2:
The patent introduces an intermediary insulating structure (fin-insulating structure) between adjacent active regions. This intermediary element acts as a barrier that prevents direct contact and potential short circuits between adjacent source/drain regions during the etching process, while allowing the overall structure to maintain scaled dimensions for high density
2Area of stationary object
If the contacted poly pitch is reduced to increase device density, then more devices can be packed in the same area, but the etching process becomes more complex and prone to bridging errors
Solution Approach 1:
The patent performs preliminary action by forming the insulating structure between adjacent active regions before the final etching process. This preliminary structuring simplifies the subsequent etching process by providing predefined isolation barriers, reducing the complexity and risk of bridging errors that would otherwise occur with aggressive pitch scaling
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances device reliability and performance by preventing short circuits and allowing for continued scaling and increased density in multi-gate devices, addressing the limitations of existing CPP scaling methods.
Implementation Method 1
a fin-insulating structure formed using a dry etching process
Data Source
AI summary
A semiconductor device includes a silicon substrate and a fin formed above the substrate. The fin provides active regions for two devices, such as gate-all-around transistors. The semiconductor device also includes a fin-insulating structure positioned to electrically isolate the active regions for the two devices. The fin-insulating structure is formed in a trench, with a first portion adjacent the fin and a second portion below the fin and extending into the substrate. The fin-insulating structure includes an oxide liner in the second portion of the trench, but not the first portion. The fin-insulating structure is further filled with an insulating material such as silicon nitride.