Fin Field Insulating Structure for Lower Parasitic Capacitance
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Solution Overview
Problem
Integrated circuit devices face challenges in achieving high operation speeds and reliability due to parasitic capacitance between adjacent conductive regions, which affect performance and power consumption.
Innovation Solution
The integrated circuit device incorporates a field insulating structure with a first buried insulating film, an insulating liner, and a second buried insulating film, including a nitride film, to reduce parasitic capacitance by overlapping the sidewalls of fin-type active regions and nanosheet stacks, with varying thicknesses and densities of silicon oxide films.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional single-layer insulating structure is used between fin-type active regions, then the device structure is simple and easy to manufacture, but parasitic capacitance between adjacent conductive regions increases, reducing operation speed and increasing power consumption
Solution Approach 1:
The insulating structure is divided into three distinct layers: a first buried insulating film (silicon oxide) contacting the fin sidewall, an insulating liner (silicon oxide with higher density), and a second buried insulating film (nitride film) spaced apart from the first film. This segmentation allows each layer to contribute differently to reducing parasitic capacitance while maintaining manufacturability through standard deposition processes.
Solution Approach 2:
The patent employs a composite insulating structure combining different materials (silicon oxide and silicon nitride) with distinct dielectric properties. The silicon oxide layers provide good interface characteristics and the nitride film provides higher dielectric strength, creating a composite structure that optimally reduces parasitic capacitance while managing electrical performance.
2Reliability
If the insulating structure is positioned closer to reduce parasitic capacitance, then operation speed improves, but manufacturing precision requirements increase due to spacing control
Solution Approach 1:
The insulating liner acts as an intermediary layer between the first buried insulating film and the second buried insulating film. This intermediate layer facilitates controlled spacing and provides a buffer zone that relaxes manufacturing precision requirements while maintaining the electrical performance benefits of reduced parasitic capacitance.
Solution Approach 2:
The patent applies different insulating materials at different locations: silicon oxide near the fin sidewall for good interface quality, silicon nitride farther away for high dielectric strength. This local differentiation optimizes both electrical performance and manufacturing robustness by placing each material where it provides maximum benefit.
Data Source
AI summary
An integrated circuit device includes a pair of fin-type active regions that extend in a first direction and are on a substrate, a gate line that is on the pair of fin-type active regions and extends in a second direction, and a field insulating structure that is between the substrate and the gate line, where the field insulating structure includes: a first buried insulating film that contacts the sidewall of each of the pair of fin-type active regions, an insulating liner that is between the pair of fin-type active regions and at least partially overlaps the first buried insulating film in a third direction, and a second buried insulating film that is between the pair of fin-type active regions and at least partially overlaps the insulating liner in the third direction, where the second buried insulating film includes a nitride film.