Semiconductor Fin Oxynitride Interface for Impurity Diffusion Control

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Solution Overview

Problem

As semiconductor devices continue to reduce minimum feature sizes for increased integration density, challenges arise in controlling diffusion of elements, dopants, and impurities within nanostructures, affecting transistor performance and reliability.

Innovation Solution

Incorporation of diffusion barrier layers, specifically a first diffusion barrier layer over nanostructures and a second diffusion barrier layer at endpoints, to inhibit the diffusion of elements and impurities, thereby maintaining control over the composition and crystal structure of channel regions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If minimum feature sizes are reduced to increase integration density, then more components can be integrated into a given area, but control over diffusion of elements, dopants, and impurities becomes difficult

Engineering Contradiction:
Improveintegration densityVSAvoidcontrol over diffusion
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

A diffusion barrier layer is introduced as an intermediary between the semiconductor layer and adjacent structures. This barrier layer selectively prevents diffusion of elements, dopants, and impurities while allowing fabrication processes to continue at reduced feature sizes, thus resolving the contradiction between increased integration density and maintained manufacturing precision

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent modifies the material composition and structural parameters by introducing a diffusion barrier layer with specific properties (selective permeability). This parameter change enables the system to maintain control over diffusion processes even as feature sizes are reduced, allowing higher integration density without sacrificing manufacturing precision

Inventive Principle:
Principle #35Parameter changes

2Reliability

If diffusion barrier layers are added to control diffusion, then transistor performance and reliability improve, but device complexity increases

Engineering Contradiction:
Improvetransistor performanceVSAvoidnumber of layers
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The diffusion barrier layer is applied selectively only where diffusion control is needed (at specific interfaces and regions), rather than throughout the entire device. This localized approach improves transistor performance and reliability while minimizing the increase in overall device complexity

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Improves transistor yield, performance, and reliability by preventing diffusion of impurities and maintaining performance characteristics of nanostructures, enhancing the fabrication process.

Implementation Method 1

Incorporation of diffusion barrier layers, specifically a first diffusion barrier layer over nanostructures and a second diffusion barrier layer at endpoints, to inhibit the diffusion of elements and impurities

Methodology Applied
Scientific EffectDiffusion barrier: Diffusion Barrier

Data Source

PatentUS20250344464A1Semiconductor device and method of forming same
Publication Date: 2025.11.06 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250344464A1 patent drawing
  • US20250344464A1 patent drawing
  • US20250344464A1 patent drawing

AI summary

In an embodiment, a method of forming a semiconductor device includes: forming a first oxide layer over a semiconductor fin structure; performing a first nitridation process to convert the first oxide layer to an oxynitride layer; depositing a silicon-containing layer over the oxynitride layer; performing a first anneal on the silicon-containing layer, wherein after performing the first anneal, the oxynitride layer has a higher nitrogen atomic concentration at an interface with the semiconductor fin structure than in a bulk region of the oxynitride layer; and forming a dummy gate structure over the silicon-containing layer.