Fin Isolation Trench Formation for Low-Aspect-Ratio CPODE
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Solution Overview
Problem
Existing isolation structures in semiconductor integrated circuits face challenges in achieving a reduced aspect ratio for continuous poly on diffusion edge (CPODE) trenches, leading to increased etching difficulty and non-uniform depths, which can result in undercut issues and degrade electrical performance.
Innovation Solution
A method is developed to form CPODE structures by selectively recessing a middle gate segment and extending the trench downward to below the substrate, removing STI features, and filling with dielectric material to increase the trench depth and reduce aspect ratio, thereby enhancing isolation between adjacent devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If existing isolation structures are used to divide active regions, then isolation between segments is achieved, but the aspect ratio of CPODE trenches increases leading to etching difficulty and non-uniform depths
Solution Approach 1:
The patent extends the CPODE trench depth into the third dimension (vertical direction) to achieve a reduced aspect ratio. By increasing the trench depth below the substrate, the horizontal width can be reduced while maintaining manufacturable aspect ratios, thereby improving etching uniformity and precision in advanced node fabrication.
Solution Approach 2:
The patent performs preliminary removal of STI features before forming the CPODE trench. This preliminary action creates a cleaner substrate surface and eliminates interference from existing isolation structures, enabling more precise and uniform trench etching at reduced aspect ratios.
2Ease of manufacture
If CPODE trenches with reduced aspect ratio are formed, then etching process window improves, but additional processing steps are required to extend trench depth
Solution Approach 1:
The patent combines multiple functions into the CPODE trench formation process: the same trench serves both as the isolation structure and as the template for subsequent dielectric fill. The extended trench depth simultaneously achieves reduced aspect ratio and provides sufficient isolation, merging form and function in a single structural element.
Solution Approach 2:
The extended CPODE trench structure serves multiple purposes: it provides electrical isolation between active regions, defines the pattern for dielectric fill, and establishes the geometric constraints for subsequent processing steps. This multi-functional design justifies the additional processing complexity by eliminating the need for separate isolation structures.
3Reliability
If trench depth is increased to reduce aspect ratio, then isolation between adjacent devices is enhanced, but more material removal is required
Solution Approach 1:
The patent selectively removes STI features and extends the trench depth only in specific regions where isolation is needed, rather than uniformly increasing trench depth across the entire wafer. This targeted extraction approach enhances isolation effectiveness while minimizing overall material removal and processing time.
Data Source
AI summary
Semiconductor structures and methods are provided. An exemplary method according to the present disclosure includes receiving a workpiece including a first semiconductor fin and a second semiconductor fin penetrating from a substrate and separated by a first isolation feature, and a gate structure intersecting the first semiconductor fin and the second semiconductor fin. The method also includes removing the gate structure and portions of the first semiconductor fin, the second semiconductor fin, and the first isolation feature disposed directly under the gate structure to form a fin isolation trench, forming a dielectric layer over the workpiece to substantially fill the fin isolation trench, and planarizing the dielectric layer to form a fin isolation structure in the fin isolation trench.