Fin Isolation Dielectric Plug for Low-Capacitance Source/Drain Scaling
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving higher device density, performance, and reducing costs, particularly in the fabrication and design of transistors, where existing technologies struggle to efficiently manage parasitic capacitance and electrical resistance.
Innovation Solution
The method involves forming semiconductor fins over a substrate, depositing isolation dielectric layers, and creating an isolation dielectric plug between the fins. This configuration allows for the enlargement of source/drain structures without touching each other, reducing electrical resistance and achieving low parasitic capacitance by sealing air gaps in the isolation dielectric plug.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If source/drain structures are enlarged to reduce electrical resistance, then electrical resistance decreases, but parasitic capacitance increases
Solution Approach 1:
An isolation dielectric plug is introduced as an intermediary element positioned between adjacent source/drain structures. This plug acts as a mediator that electrically isolates the enlarged source/drain regions, preventing capacitive coupling between them. The plug allows the source/drain structures to be enlarged for lower resistance while simultaneously blocking the harmful parasitic capacitance that would otherwise increase with larger structure size.
Solution Approach 2:
The isolation dielectric plug segments the continuous electrical field between adjacent source/drain structures by introducing a dielectric barrier. This segmentation divides the electrical interaction into isolated regions, allowing each source/drain structure to be independently enlarged without direct capacitive coupling to neighbors, thus reducing resistance while controlling parasitic capacitance.
2Productivity
If device density is increased to improve performance, then device density increases, but fabrication complexity increases
Solution Approach 1:
The formation of the isolation dielectric plug is merged with the existing shallow trench isolation (STI) process flow. The plug is formed using the same deposition and planarization steps already required for STI, combining multiple functions into a unified process sequence. This merging allows high device density to be achieved without proportionally increasing fabrication complexity, as the additional isolation function is integrated into existing manufacturing steps.
3Object-generated harmful factors
If air gaps are sealed in isolation dielectric plug to reduce parasitic capacitance, then parasitic capacitance decreases, but manufacturing precision requirements increase
Solution Approach 1:
The isolation dielectric plug structure utilizes the natural planarization provided by the chemical mechanical polishing (CMP) process to automatically seal air gaps. As the overlying dielectric layer is planarized, it naturally flows into and fills any voids or air gaps within the plug, sealing them without requiring additional precision-controlled steps. This self-service mechanism reduces parasitic capacitance while minimizing the manufacturing precision burden on the plug formation process itself.
Data Source
AI summary
A method for forming a semiconductor device is provided. The method includes forming first and second semiconductor fins over a semiconductor substrate; depositing a first isolation dielectric layer over the first and second semiconductor fins, the first isolation dielectric layer having a trench between the first and second semiconductor fins; depositing a second isolation dielectric layer having a first portion over a top surface of the first isolation dielectric layer and a second portion lining the trench of the first isolation dielectric layer; performing a chemical mechanical polish process to remove the first portion of the second isolation dielectric layer, while leaving the second portion of the second isolation dielectric layer to form an isolation dielectric plug between the first and second semiconductor fins; and after forming the isolation dielectric plug, forming first and second epitaxial structures over the first and second semiconductor fins.