Semiconductor Fin Isolation Etching to Minimize Fin Loss

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Solution Overview

Problem

Existing vertical field-effect transistors face issues with fin loss and high contact resistance due to lateral etching in the fin cut process, leading to current leakage and reduced process windows for contact landing, which affect the performance and reliability of semiconductor devices.

Innovation Solution

A method is introduced to reduce the loading effect by creating a height difference in the BARC layer and depositing a coating layer to slow down lateral etching, while performing vertical etching to form semiconductor fins with varied profiles, ensuring better overlap with gate structures and larger process windows.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If lateral etching is performed in the fin cut process, then the fin structure is formed, but fin loss occurs and contact resistance increases

Engineering Contradiction:

Improvefin structure formationVSAvoidfin loss and contact resistance

Core Design Contradiction:

Manufacturing precisionVSReliability

Solution Approach 1:

A protective coating layer is deposited on the sidewalls of the fin structure before the fin cut etching process. This preliminary protective action prevents the harmful lateral etching from reaching the fin, thereby avoiding fin loss and reducing contact resistance while still allowing the fin structure to be formed through lateral etching.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The protective coating layer acts as an intermediary barrier between the lateral etching process and the fin structure. It mediates the interaction by being selectively removed after serving its protective function, allowing the fin to be formed without direct exposure to the harmful lateral etching.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Ease of manufacture

If the BARC layer is made uniform, then the process is simple, but the loading effect is not reduced

Engineering Contradiction:

ImproveBARC layer formationVSAvoidloading effect reduction

Core Design Contradiction:

Ease of manufactureVSManufacturing precision

Solution Approach 1:

The BARC layer is formed with different thicknesses in different regions: a first thickness in the dense region and a second thickness in the isolation region. This local variation in thickness reduces the loading effect during etching, with the thinner BARC layer in isolation regions experiencing less etching load compared to the thicker BARC layer in dense regions.

Inventive Principle:

Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the electrical properties, reliability, and yield of semiconductor devices by minimizing fin loss and contact resistance, and improving the fin formation and contact landing processes.

Implementation Method 1

existing vertical field-effect transistors have not been satisfactory in all aspects, and similar developments of tools and methods for improving the performance of the semiconductor device are needed

Methodology Applied

Scientific EffectLateral etching:

Implementation Method 2

performing vertical etching to form semiconductor fins with varied profiles

Methodology Applied

Scientific EffectVertical etching:

Implementation Method 3

A method is introduced to reduce the loading effect by creating a height difference in the BARC layer

Methodology Applied

Scientific EffectLoading effect:

Implementation Method 4

depositing a coating layer to slow down lateral etching, while performing vertical etching to form semiconductor fins with varied profiles

Methodology Applied

Scientific EffectLateral etching protection:

Implementation Method 5

performing vertical etching to form semiconductor fins with varied profiles, ensuring better overlap with gate structures

Methodology Applied

Scientific EffectMaterial removal:

Data Source

PatentUS11784055B2Method of forming semiconductor device with fin isolation

Publication Date: 2023.10.10 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A method includes following steps. A substrate is etched using a hard mask as an etch mask to form a fin. A bottom anti-reflective coating (BARC) layer is over the fin. A recess is formed in the BARC layer to expose a first portion of the hard mask. A protective coating layer is formed at least on a sidewall of the recess in the BARC layer. A first etching step is performed to remove the first portion of the hard mask to expose a first portion of the fin, while leaving a second portion of the fin covered under the protective coating layer and the BARC layer. A second etching step is performed to lower a top surface of the first portion of the fin to below a top surface of the second portion of the fin.