Fin Isolation Continuous With Gate Cut Plugs for Tighter IC Spacing
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Solution Overview
Problem
The challenge of maintaining mobility improvement and short channel control in microelectronic devices as device dimensions scale below the 10 nanometer node, particularly in multi-gate and nanowire transistors, is exacerbated by the constraints on lithographic processes used to pattern features, leading to a trade-off between critical dimension and spacing.
Innovation Solution
The implementation of fin isolation regions continuous with gate cut plugs, where the metal gate cut process is performed subsequent to gate dielectric and work function metal deposition, allowing for a 'plug-last' approach that reduces interference with metal gate processing and ensures a seamless work function metal deposition, thereby alleviating space constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional tri-gate fabrication processes are used on bulk silicon substrates, then manufacturing cost is reduced and fabrication complexity is lowered, but mobility improvement and short channel control deteriorate at dimensions below 10 nanometer node
Solution Approach 1:
The patent transitions from planar 2D transistor structures to three-dimensional FinFET structures with vertical channels. The fin structure extends into the third dimension (depth), creating a non-planar channel that provides superior gate control over the channel while maintaining scalability. This dimensional change enables continued short channel control as device dimensions scale below 10 nanometer node.
2Quantity of substance
If feature dimensions are reduced to increase device density, then capacity increases, but lithographic process constraints worsen due to the trade-off between critical dimension and spacing
Solution Approach 1:
The FinFET structure utilizes vertical fins extending from the substrate surface, transforming the device architecture from a planar layout to a three-dimensional structure. This vertical dimension allows for increased effective channel area and device density without proportionally reducing lithographic feature sizes, as the critical dimensions are defined by the fin width and height rather than purely by planar gate dimensions.
3Reliability
If gate cut plugs are formed before metal gate deposition, then gate isolation is achieved, but metal gate processing is interfered with and voids may form during metal fill
Solution Approach 1:
The patent inverts the conventional sequence of operations by forming the metal gate structure first and then creating the gate cut plugs subsequently. This reverse sequencing ensures that the metal gate deposition process occurs on continuous, unbroken gate structures, eliminating the risk of void formation during metal fill. The gate cut plugs are then formed to provide the necessary isolation after the metal gate is already in place.
4Quantity of substance
If tighter spacing is implemented to increase device density, then capacity increases, but metal gate processing becomes more difficult and may result in voids
Solution Approach 1:
By inverting the process sequence to form metal gates before gate cut plugs, the patent eliminates the spacing constraints that would otherwise limit metal gate processing. The continuous gate structure allows for reliable metal deposition even at tight spacings, and the subsequent formation of gate cut plugs provides isolation without interfering with the already-deposited metal gate, thereby enabling tighter spacing while maintaining manufacturing ease.
Data Source
AI summary
Integrated circuit structures having fin isolation regions continuous with gate cut plugs are described. In an example, an integrated circuit structure includes a vertical stack of horizontal nanowires or a fin over a first sub-fin. A gate structure is over the vertical stack of horizontal nanowires or the fin and on the first sub-fin. A dielectric structure is laterally spaced apart from the gate structure. The dielectric structure is not over a channel structure but is on a second sub-fin. A gate cut is between the gate structure and the dielectric structure. A dielectric gate cut plug is in the gate cut. The dielectric gate cut plug is continuous with the dielectric structure.