Fin-Isolation Insulating Portions for Integrated Circuit Devices
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Solution Overview
Problem
Integrated circuit devices face challenges in reducing the area occupied by wires and contacts while maintaining insulation distance, which affects operational speed and accuracy as they are downscaled.
Innovation Solution
The design incorporates fin-type active regions and fin-isolation insulating portions on a substrate, with specific materials and structures to optimize the layout and stress application, allowing for reduced area usage without compromising insulation and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the area of the element region is reduced due to down-scaling, then the integrated circuit device achieves higher integration, but the insulation distance between wires and contacts becomes insufficient
Solution Approach 1:
The patent introduces fin-isolation insulating portions that extend in the vertical dimension between adjacent fin-type active regions. This vertical isolation structure provides additional insulation distance without occupying horizontal area, thereby resolving the contradiction between high integration density and sufficient insulation distance in down-scaled devices.
Solution Approach 2:
The fin-isolation insulating portions act as intermediary structures between adjacent fin-type active regions. These insulating portions mediate the electrical isolation between neighboring transistors, enabling sufficient insulation distance to be achieved within the constrained horizontal area of down-scaled integrated circuits.
2Area of stationary object
If the area occupied by wires and contacts is reduced, then the element region area increases, but the operational speed and accuracy may be compromised
Solution Approach 1:
The patent applies different materials to different regions of the fin-isolation insulating portions. Specifically, a first material is used in a first region and a second material is used in a second region, allowing local optimization of electrical properties. This enables the structure to maintain operational accuracy by providing appropriate electrical characteristics in different areas while maximizing the element region area.
3Reliability
If fin-isolation insulating portions are added between gate structures, then insulation distance is improved, but device complexity increases
Solution Approach 1:
The patent combines the fin-isolation insulating portions with the existing fin-type active region structure. The insulating portions are integrated into the same vertical stack as the active regions, sharing the same formation processes and spatial arrangement. This merging approach provides improved insulation distance while minimizing the increase in device complexity by reusing existing structural elements and manufacturing steps.
Data Source
AI summary
An integrated circuit device includes a substrate from which a plurality of fin-type active regions protrude, the plurality of fin-type active regions extending in parallel to one another in a first direction, and a plurality of gate structures and a plurality of fin-isolation insulating portions extending on the substrate in a second direction crossing the first direction and at a constant pitch in the first direction, wherein a pair of fin-isolation insulating portions from among the plurality of fin-isolation insulating portions are between a pair of gate structures from among the plurality of gate structures, and the plurality of fin-type active regions include a plurality of first fin-type regions and a plurality of second fin-type regions.