Fin Isolation Metal Plug Layout for Void-Free Nanowire Gates
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Solution Overview
Problem
The challenge in integrated circuit manufacturing lies in the complexity of fin trim isolation (FTI) processes as gate pitch and FIN pitch shrink, leading to interference with metal gate processes, device variability, and constraints on lithographic processes, particularly in multi-gate and nanowire transistors below the 10 nanometer node.
Innovation Solution
Implementing a 'plug-last' approach where the FTI opening is backfilled with metal instead of dielectric material, reducing processing operations and minimizing the negative impact on metal gate processing, and allowing for seamless work function metal deposition without voids.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional dielectric material is used to backfill FTI openings, then isolation between fins is achieved, but metal fill capability is poor and processing complexity increases
Solution Approach 1:
The patent changes the material parameter of the FTI opening backfill from dielectric material to metal material. This parameter change transforms the filling process into a metal deposition process that is more compatible with existing metal gate processes, improving metal fill capability while maintaining isolation effectiveness through the conductive nature of the metal fill.
Solution Approach 2:
Instead of following the conventional approach of backfilling FTI openings with dielectric material first and then adding metal gates, the patent inverts the sequence by using metal material for the backfill. This inversion allows the metal fill process to serve dual purposes: providing isolation and preparing the surface for subsequent work function metal deposition without creating voids or interface issues.
2Manufacturing precision
If FTI process complexity increases due to shrinking gate pitch and FIN pitch, then finer patterning is achieved, but interference with metal gate processes and device variability increase
Solution Approach 1:
The patent merges the FTI backfill process with the metal gate deposition process by using metal material for the backfill. This consolidation reduces the number of separate processing steps, eliminating interference between dielectric filling and metal gate processes while maintaining the required patterning precision for shrinking gate and FIN pitches.
Solution Approach 2:
The patent extracts the FTI backfill step from the conventional dielectric filling sequence and replaces it with metal deposition. This extraction simplifies the overall process flow by removing unnecessary dielectric material deposition and etching steps, reducing process complexity while maintaining or improving patterning precision through the metal deposition process.
3Reliability
If dielectric material is used for FTI backfill, then isolation is provided, but voids form during metal deposition and work function metal deposition is compromised
Solution Approach 1:
The patent changes the material parameter of the FTI backfill from dielectric to metal, which fundamentally alters the deposition characteristics. Metal deposition provides a continuous, void-free layer that serves as an ideal substrate for work function metal deposition, ensuring high-quality interface formation while maintaining the isolation function through the conductive metal fill.
Data Source
AI summary
Integrated circuit structures having conductive structures in fin isolation regions are described. In an example, an integrated circuit structure includes a vertical stack of horizontal nanowires over a sub-fin. The integrated circuit structure also includes a gate structure. The gate structure includes a first gate structure portion over the vertical stack of horizontal nanowires, a second gate structure portion laterally adjacent to the first gate structure portion, wherein the second gate structure portion is not over a channel structure, and a gate cut between the first gate structure portion and the second gate structure portion.