Fin Layout Rectangularization for Gate-All-Around Channel Control
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Solution Overview
Problem
As transistor dimensions are scaled down to sub 10-15 nm technology nodes, FinFETs face challenges in achieving full control over the channel region due to the gate structure not covering the bottom side, leading to issues like short-channel effects and reduced device performance.
Innovation Solution
The method involves forming fin structures with mandrel patterns and subsequent etching to create sidewall spacers, followed by patterning and removing mandrel layers to form fin structures, and then using mask patterns to cut and shape the fins, incorporating dummy active regions and fin-end gate cut patterns to achieve full gate control over the channel region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If FinFET gate structure is used with gate adjacent to three side surfaces of channel region, then device density and controllability are improved, but short-channel effects increase due to incomplete gate control over the channel region
Solution Approach 1:
The patent transitions from a planar gate structure to a three-dimensional gate-all-around structure that wraps completely around the channel region. This dimensional change allows the gate to control the channel from all directions (top, bottom, and lateral surfaces), achieving full depletion and eliminating short-channel effects while maintaining high device density.
Solution Approach 2:
The channel region is segmented into multiple fins or nanowires, each surrounded by its own gate structure. This segmentation allows independent gate control over each channel segment, ensuring complete electrostatic control while increasing overall device density through parallel operation of multiple segments.
2Productivity
If transistor dimensions are scaled down to sub 10-15 nm nodes, then device density and performance are improved, but fabrication precision requirements increase significantly
Solution Approach 1:
The patent employs preliminary patterning actions where mandrel structures and sacrificial layers are formed first to define the channel region geometry before the actual gate material deposition. This preliminary structuring enables precise control of sub-10nm dimensions through self-aligned processes, reducing the burden on subsequent fabrication steps.
Solution Approach 2:
The fabrication process uses nested structuring where inner sacrificial layers are formed within outer mandrel structures, which are themselves defined within larger patterned regions. This nested approach allows multiple dimensional constraints to be imposed sequentially, achieving sub-10nm precision through cumulative self-alignment rather than single-step lithography.
3Reliability
If GAA FET structure with complete gate surrounding is implemented, then short-channel effects are reduced and sub-threshold current swing is improved, but device complexity increases
Solution Approach 1:
The gate structure serves multiple functions simultaneously: it provides electrostatic control over the channel, acts as a barrier to short-channel effects, enables steep sub-threshold swing, and functions as an interconnect element. This multi-functionality reduces the need for additional separate structures, thereby managing complexity while achieving superior electrical characteristics.
Solution Approach 2:
The patent merges the gate structure with the channel formation process, where the gate material is deposited conformally around the channel region in a single integrated sequence. This combining of gate and channel structuring operations reduces the number of discrete fabrication steps and simplifies the overall device architecture despite the three-dimensional geometry.
Data Source
AI summary
In a method of manufacturing a semiconductor device, a layout is prepared. The layout includes active region patterns, each of the active region patterns corresponding to one or two fin structures, first fin cut patterns and second fin cut patterns. At least one pattern selected from the group consisting of the first fin cut patterns and the second fin cut patterns has a non-rectangular shape. The layout is modified by adding one or more dummy active region patterns and by changing the at least one pattern to be a rectangular pattern. Base fin structures are formed according to a modified layout including the active region patterns and the dummy active region patterns. Part of the base fin structures is removed according to one of a modified layout of the first fin cut patterns and a modified layout of the second fin cut patterns.