Fin LDMOS Gate Air Gap Layout for Leakage and RF Performance
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Solution Overview
Problem
Current LDMOS devices face challenges with current leakage and breakdown voltage control as they scale down, particularly when integrated with FinFET devices, necessitating improved fabrication techniques to enhance performance.
Innovation Solution
The implementation of a lateral diffused metal oxide semiconductor (LDMOS) device design featuring fin-shaped structures, shallow trench isolation, and air gaps between gate structures, which includes forming fin-shaped structures on a substrate, shallow trench isolation between them, and air gaps between gate structures to reduce parasitic capacitance and improve frequency performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If LDMOS devices are scaled down to reduce size, then device integration density is improved, but current leakage and breakdown voltage control deteriorate
Solution Approach 1:
The device is divided into multiple fins (first fin-shaped structure, second fin-shaped structure, third fin-shaped structure) with isolation regions between them. This segmentation allows each fin to be independently controlled and managed, reducing the overall current leakage while maintaining high integration density. The STI regions create electrical isolation between adjacent fins, preventing leakage paths.
Solution Approach 2:
Shallow trench isolation (STI) structures are introduced as intermediary elements between the fin-shaped structures. These STI regions act as mediators that provide electrical isolation and control the breakdown voltage characteristics. The air gaps between gate structures also serve as intermediaries to reduce parasitic capacitance and improve voltage control.
2Speed
If air gaps are introduced between gate structures to reduce parasitic capacitance, then frequency performance is improved, but device complexity increases
Solution Approach 1:
Air gaps are introduced in the vertical dimension between gate structures rather than increasing horizontal separation. This dimensional approach reduces parasitic capacitance between gates without significantly increasing the device footprint. The air gaps are formed by controlling the etch depth to expose the substrate between fins, creating vertical spacing that effectively reduces capacitance while maintaining a compact planar layout.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces parasitic capacitance and significantly enhances cut-off frequency (FT) and maximum oscillation frequency (Fmax) by creating an air gap between gate structures, thereby addressing the issues of current leakage and breakdown voltage control.
Implementation Method 1
reduces parasitic capacitance and significantly enhances cut-off frequency (FT) and maximum oscillation frequency (Fmax) by creating an air gap between gate structures
Data Source
AI summary
A lateral diffused metal oxide semiconductor (LDMOS) device includes a first fin-shaped structure on a substrate, a second fin-shaped structure adjacent to the first fin-shaped structure, a shallow trench isolation (STI) between the first fin-shaped structure and the second fin-shaped structure, a first gate structure on the first fin-shaped structure, a second gate structure on the second fin-shaped structure, and an air gap between the first gate structure and the second gate structure.