Semiconductor Fin Loop with Diffusion Break for Leakage Control
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Solution Overview
Problem
In finFETs, the short channel effect due to reduced separation between source and drain regions leads to leakage current issues and poor epitaxial growth, with existing solutions like T-shaped isolation trenches causing asymmetric source and drains or adding complexity with additional processing steps.
Innovation Solution
A semiconductor fin loop is created by connecting ends of semiconductor fins with a connector fin, forming a diffusion break that isolates the source or drain, allowing for epitaxial growth and reducing leakage by maintaining semiconductor material under the dummy gate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the channel length of FETs is scaled down to improve switching speed and increase device density, then the operating speed and density are improved, but the separation between source and drain regions decreases leading to short channel effects and increased leakage current
Solution Approach 1:
The source and drain regions are segmented by introducing a diffusion break structure that physically divides the channel into separate sections. This segmentation allows independent control of source and drain potentials, preventing the drain potential from adversely affecting the source region and channel, thus reducing leakage current while maintaining short channel dimensions for high speed operation
Solution Approach 2:
A dummy gate structure is introduced as an intermediary element positioned over the diffusion break. This dummy gate acts as a mediator that helps maintain proper electrical isolation between source and drain regions while allowing the channel to remain short for high-speed operation. The dummy gate structure provides a reference potential that stabilizes the electrical characteristics of the finFET
2Reliability
If T-shaped isolation trenches are used to create diffusion breaks, then leakage is reduced, but the source and drain become asymmetric and the process complexity increases
Solution Approach 1:
The invention intentionally introduces a controlled asymmetric element (the dummy gate over the diffusion break) to achieve symmetric electrical characteristics in the source and drain regions. By placing the dummy gate structure centrally over the diffusion break, the electrical fields in both source and drain regions are balanced, resulting in symmetric device performance despite the physical asymmetry of the diffusion break structure
Solution Approach 2:
The diffusion break structure with dummy gate is formed early in the fabrication process, before the actual source and drain epitaxial growth. This preliminary action establishes the electrical isolation and field control mechanisms in advance, allowing subsequent processing steps to proceed with simplified alignment requirements and reducing overall process complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the fin formation process, enhances epitaxial growth, and reduces leakage by providing a stable epitaxial growth surface, improving the functionality and reliability of finFETs.
Implementation Method 1
allowing for epitaxial growth and reducing leakage by maintaining semiconductor material under the dummy gate
Data Source
AI summary
A finFET includes a source or a drain including: a first semiconductor fin extending parallel to a second semiconductor fin, and a semiconductor connector fin creating a first semiconductor fin loop by connecting an end of the first semiconductor fin to an end of the second semiconductor fin. A diffusion break isolates the source or the drain, and is positioned about the first semiconductor connector fin and the ends of the first semiconductor fin and the second semiconductor fin. The semiconductor connector fin provides an epitaxial growth surface adjacent the diffusion break. A related method and IC structure are also disclosed.