Fin Source/Drain Low-k Dielectric Deposition for Faster Response

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Solution Overview

Problem

The semiconductor industry faces challenges in reducing capacitance in semiconductor devices to improve device response time, as existing dielectric materials have high dielectric constants, leading to increased capacitance and reduced performance.

Innovation Solution

The use of dielectric layers with a dielectric constant in the range of 2.0 to 3.5, formed using capacitive or inductive coupling plasma techniques, such as boron nitride films or silicon dioxide with Si-CH3 bonds, is implemented to decrease capacitance and enhance device response time.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If existing dielectric materials with high dielectric constants are used, then the device structure is simple and easy to manufacture, but the capacitance increases and device response time decreases

Engineering Contradiction:
Improvedevice response timeVSAvoidcapacitance
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent changes the dielectric constant parameter of the material from high (conventional) to low (2.0-3.5 range) to reduce capacitance. This is achieved by selecting specific materials like boron nitride or silicon dioxide with controlled bond structures that inherently possess lower dielectric constants, directly addressing the capacitance issue while maintaining manufacturing feasibility

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent employs composite dielectric structures combining multiple layers with different dielectric constants. By stacking layers with varying k-values (e.g., low-k materials like boron nitride combined with other dielectrics), the overall capacitance is reduced while maintaining the necessary electrical performance and structural integrity for device operation

Inventive Principle:
Principle #40Composite materials

2Reliability

If low-k dielectric materials are used to reduce capacitance, then device response time improves, but the manufacturing process complexity increases

Engineering Contradiction:
Improvedevice response timeVSAvoidmanufacturing process
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies preliminary protective actions during the deposition of low-k dielectric layers by forming protective films or using protective gas environments during manufacturing. This prevents damage to the sensitive low-k materials during subsequent processing steps, reducing manufacturing complexity while maintaining the low-capacitance benefits

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces intermediary protective layers or barrier films between the low-k dielectric materials and other device components. These intermediary layers protect the low-k materials from damage during manufacturing and operation, simplifying the overall process by preventing failures rather than requiring complex repair or rework procedures

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively reduces capacitance, thereby increasing device response time and improving overall semiconductor device performance by using low-k dielectric materials like boron nitride and silicon dioxide with specific bond structures.

Implementation Method 1

forming a first dielectric layer over the source/drain region and the dummy gate, the first dielectric layer having a dielectric constant of 3.5 or less, the first dielectric layer including boron nitride; and forming an opening by removing the dummy gate. In an embodiment, forming the first dielectric layer includes a plasma process using capacitive coupling plasma

Methodology Applied
Scientific EffectCapacitive coupling plasma: Plasma

Implementation Method 2

forming a first dielectric layer over the source/drain region and the dummy gate, the first dielectric layer having a dielectric constant of 3.5 or less, the first dielectric layer including boron nitride; and forming an opening by removing the dummy gate. In an embodiment, forming the first dielectric layer includes a plasma process using inductive coupling plasma

Methodology Applied
Scientific EffectInductive coupling plasma: Plasma

Data Source

PatentUS20230268225A1Semiconductor device and method of forming the same
Publication Date: 2023.08.24 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20230268225A1 patent drawing
  • US20230268225A1 patent drawing
  • US20230268225A1 patent drawing

AI summary

A method for manufacturing a semiconductor device includes forming a source/drain region on a semiconductor fin. The source/drain region is adjacent to a dummy gate. The method further includes forming a first dielectric layer over the source/drain region and the dummy gate. The first dielectric layer has a dielectric constant of 3.5 or less. The first dielectric layer may include boron nitride or silicon dioxide with Si-CH3 bonds.