Fin Memory Cell Structure for Disturbance-Free Scaling
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Solution Overview
Problem
In nonvolatile semiconductor storage devices, existing memory cells face challenges in preventing charge injection into unintended cells and minimizing disturbances due to unintended charge injection when high charge storage gate voltage is applied, while also requiring downsizing to increase memory cell density.
Innovation Solution
The memory cell design includes a fin structure with a memory gate and select gate structures, where the fin's height and width configuration forms a depleted layer to prevent charge injection, and the select gate structures block electrical connections to reduce potential differences, allowing for downsizing without increasing disturbance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high charge storage gate voltage is applied to the memory gate line to inject charge into the charge storage layer, then charge injection is achieved in the selected memory cell, but unintended charge injection and disturbance occur in non-selected memory cells sharing the same memory gate line
Solution Approach 1:
The patent divides the gate control into segmented structures: memory gate electrodes for charge storage and select gate electrodes for channel control. This segmentation allows independent control of charge injection (via memory gate) and channel conduction (via select gates), preventing unintended charge injection in non-selected cells while maintaining reliability in selected cells.
Solution Approach 2:
The patent applies different voltage conditions locally to different regions: high memory gate voltage is applied only to selected memory gate electrodes corresponding to active memory cells, while non-selected memory gate electrodes remain at low voltage. This local differentiation ensures charge injection occurs only where needed, eliminating disturbance in non-selected cells.
2Device complexity
If conventional memory cell structures are used with shared memory gate lines, then device complexity is reduced, but disturbance prevention becomes difficult
Solution Approach 1:
The gate structure is segmented into memory gate electrodes and select gate electrodes with distinct functions. Memory gate electrodes are shared across rows for charge storage control, while select gate electrodes provide local column-specific control. This segmentation maintains the efficiency of shared lines while adding the capability to prevent disturbance through selective activation.
Solution Approach 2:
Before charge injection can occur, the select gates must first be activated to establish proper channel conditions. This preliminary action ensures that even if high memory gate voltage is applied to non-selected cells, the depleted channel regions prevent charge injection, thus preventing disturbance before it can occur.
3Productivity
If memory cell size is reduced to increase density, then storage capacity increases, but disturbance suppression becomes more challenging
Solution Approach 1:
The patent transitions from planar gate structures to three-dimensional fin-type semiconductor substrates with vertical channel regions. This dimensional change allows memory gate electrodes to wrap around the fin structure, creating surrounded channel regions that enhance charge confinement. The vertical dimension provides additional control over charge injection paths, enabling disturbance suppression even in highly dense configurations.
Solution Approach 2:
The memory gate electrode structure is nested around the fin-type semiconductor substrate, with the gate wrapping around three sides of the vertical fin. This nested configuration creates surrounded channel regions that confine charge carriers, preventing unintended charge injection into adjacent cells and suppressing disturbance while maintaining high density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively prevents charge injection into unintended memory cells, reduces disturbance, and enables downsizing to increase memory cell density by forming depleted layers entirely within the fin, thereby enhancing operational efficiency and storage capacity.
Implementation Method 1
high memory gate voltage is applied to a memory gate electrode of the memory gate structure so that charge is injected into the charge storage layer due to a quantum tunneling effect caused by a large voltage difference between the bit voltage and the memory gate voltage
Data Source
Figure 1
Figure 2
Figure 3A~3B
AI summary
When a memory cell (MC) is downsized by reducing the distance between a drain region (12a) and a source region (12b) on the surface of a fin (S2) with a high impurity concentration inside the fin (S2), the shape of the fin (S2) can be set such that a potential difference between a memory gate electrode (MG) and the fin (S2) is reduced to suppress the occurrence of disturbance. Accordingly, the memory cell (MC) achieves downsizing and suppression of the occurrence of disturbance.